SURF  1.0
Generics | Ports | Libraries | Use Clauses
SrpV3AxiLite Entity Reference
protocols » srp
+ Inheritance diagram for SrpV3AxiLite:
+ Collaboration diagram for SrpV3AxiLite:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
INT_PIPE_STAGES_G  natural range 0 to 16 := 1
PIPE_STAGES_G  natural range 0 to 16 := 1
FIFO_PAUSE_THRESH_G  positive range 1 to 511 := 256
TX_VALID_THOLD_G  positive := 1
SLAVE_READY_EN_G  boolean := false
GEN_SYNC_FIFO_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
AXIL_CLK_FREQ_G  real := 156 . 25E + 6
AXI_STREAM_CONFIG_G  AxiStreamConfigType := ssiAxiStreamConfig ( 2 )

Ports

sAxisClk   in sl
sAxisRst   in sl
sAxisMaster   in AxiStreamMasterType
sAxisSlave   out AxiStreamSlaveType
sAxisCtrl   out AxiStreamCtrlType
mAxisClk   in sl
mAxisRst   in sl
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
axilClk   in sl
axilRst   in sl
mAxilWriteMaster   out AxiLiteWriteMasterType
mAxilWriteSlave   in AxiLiteWriteSlaveType
mAxilReadMaster   out AxiLiteReadMasterType
mAxilReadSlave   in AxiLiteReadSlaveType

Detailed Description

See also
entity

Definition at line 36 of file SrpV3AxiLite.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 38 of file SrpV3AxiLite.vhd.

◆ INT_PIPE_STAGES_G

INT_PIPE_STAGES_G natural range 0 to 16 := 1
Generic

Definition at line 39 of file SrpV3AxiLite.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G natural range 0 to 16 := 1
Generic

Definition at line 40 of file SrpV3AxiLite.vhd.

◆ FIFO_PAUSE_THRESH_G

FIFO_PAUSE_THRESH_G positive range 1 to 511 := 256
Generic

Definition at line 41 of file SrpV3AxiLite.vhd.

◆ TX_VALID_THOLD_G

TX_VALID_THOLD_G positive := 1
Generic

Definition at line 42 of file SrpV3AxiLite.vhd.

◆ SLAVE_READY_EN_G

SLAVE_READY_EN_G boolean := false
Generic

Definition at line 43 of file SrpV3AxiLite.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 44 of file SrpV3AxiLite.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 45 of file SrpV3AxiLite.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 46 of file SrpV3AxiLite.vhd.

◆ AXIL_CLK_FREQ_G

AXIL_CLK_FREQ_G real := 156 . 25E + 6
Generic

Definition at line 47 of file SrpV3AxiLite.vhd.

◆ AXI_STREAM_CONFIG_G

AXI_STREAM_CONFIG_G AxiStreamConfigType := ssiAxiStreamConfig ( 2 )
Generic

Definition at line 48 of file SrpV3AxiLite.vhd.

◆ sAxisClk

sAxisClk in sl
Port

Definition at line 51 of file SrpV3AxiLite.vhd.

◆ sAxisRst

sAxisRst in sl
Port

Definition at line 52 of file SrpV3AxiLite.vhd.

◆ sAxisMaster

sAxisMaster in AxiStreamMasterType
Port

Definition at line 53 of file SrpV3AxiLite.vhd.

◆ sAxisSlave

sAxisSlave out AxiStreamSlaveType
Port

Definition at line 54 of file SrpV3AxiLite.vhd.

◆ sAxisCtrl

sAxisCtrl out AxiStreamCtrlType
Port

Definition at line 55 of file SrpV3AxiLite.vhd.

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 57 of file SrpV3AxiLite.vhd.

◆ mAxisRst

mAxisRst in sl
Port

Definition at line 58 of file SrpV3AxiLite.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 59 of file SrpV3AxiLite.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType
Port

Definition at line 60 of file SrpV3AxiLite.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 62 of file SrpV3AxiLite.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 63 of file SrpV3AxiLite.vhd.

◆ mAxilWriteMaster

mAxilWriteMaster out AxiLiteWriteMasterType
Port

Definition at line 64 of file SrpV3AxiLite.vhd.

◆ mAxilWriteSlave

mAxilWriteSlave in AxiLiteWriteSlaveType
Port

Definition at line 65 of file SrpV3AxiLite.vhd.

◆ mAxilReadMaster

mAxilReadMaster out AxiLiteReadMasterType
Port

Definition at line 66 of file SrpV3AxiLite.vhd.

◆ mAxilReadSlave

mAxilReadSlave in AxiLiteReadSlaveType
Port

Definition at line 67 of file SrpV3AxiLite.vhd.

◆ ieee

ieee
Library

Definition at line 24 of file SrpV3AxiLite.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 25 of file SrpV3AxiLite.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 26 of file SrpV3AxiLite.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 27 of file SrpV3AxiLite.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 29 of file SrpV3AxiLite.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 30 of file SrpV3AxiLite.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 31 of file SrpV3AxiLite.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 32 of file SrpV3AxiLite.vhd.

The documentation for this class was generated from the following file: