SURF  1.0
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SrpV3Axi Entity Reference
protocols » srp
+ Inheritance diagram for SrpV3Axi:
+ Collaboration diagram for SrpV3Axi:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>
AxiPkg  Package <AxiPkg>
AxiDmaPkg  Package <AxiDmaPkg>
SrpV3Pkg  Package <SrpV3Pkg>

Generics

TPD_G  time := 1 ns
PIPE_STAGES_G  natural range 0 to 16 := 0
FIFO_PAUSE_THRESH_G  positive range 1 to 511 := 256
TX_VALID_THOLD_G  positive := 1
SLAVE_READY_EN_G  boolean := true
GEN_SYNC_FIFO_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
AXI_CLK_FREQ_G  real := 156 . 25E + 6
AXI_CONFIG_G  AxiConfigType := ( 33 , 4 , 1 , 8 )
AXI_BURST_G  slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G  slv ( 3 downto 0 ) := " 1111 "
ACK_WAIT_BVALID_G  boolean := true
AXI_STREAM_CONFIG_G  AxiStreamConfigType := ssiAxiStreamConfig ( 2 )
UNALIGNED_ACCESS_G  boolean := false
BYTE_ACCESS_G  boolean := false
WRITE_EN_G  boolean := true
READ_EN_G  boolean := true

Ports

sAxisClk   in sl
sAxisRst   in sl
sAxisMaster   in AxiStreamMasterType
sAxisSlave   out AxiStreamSlaveType
sAxisCtrl   out AxiStreamCtrlType
mAxisClk   in sl
mAxisRst   in sl
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
axiClk   in sl
axiRst   in sl
axiWriteMaster   out AxiWriteMasterType
axiWriteSlave   in AxiWriteSlaveType
axiReadMaster   out AxiReadMasterType
axiReadSlave   in AxiReadSlaveType

Detailed Description

See also
entity

Definition at line 35 of file SrpV3Axi.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 37 of file SrpV3Axi.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G natural range 0 to 16 := 0
Generic

Definition at line 38 of file SrpV3Axi.vhd.

◆ FIFO_PAUSE_THRESH_G

FIFO_PAUSE_THRESH_G positive range 1 to 511 := 256
Generic

Definition at line 39 of file SrpV3Axi.vhd.

◆ TX_VALID_THOLD_G

TX_VALID_THOLD_G positive := 1
Generic

Definition at line 40 of file SrpV3Axi.vhd.

◆ SLAVE_READY_EN_G

SLAVE_READY_EN_G boolean := true
Generic

Definition at line 41 of file SrpV3Axi.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 42 of file SrpV3Axi.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 43 of file SrpV3Axi.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 44 of file SrpV3Axi.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 156 . 25E + 6
Generic

Definition at line 45 of file SrpV3Axi.vhd.

◆ AXI_CONFIG_G

AXI_CONFIG_G AxiConfigType := ( 33 , 4 , 1 , 8 )
Generic

Definition at line 46 of file SrpV3Axi.vhd.

◆ AXI_BURST_G

AXI_BURST_G slv ( 1 downto 0 ) := " 01 "
Generic

Definition at line 47 of file SrpV3Axi.vhd.

◆ AXI_CACHE_G

AXI_CACHE_G slv ( 3 downto 0 ) := " 1111 "
Generic

Definition at line 48 of file SrpV3Axi.vhd.

◆ ACK_WAIT_BVALID_G

ACK_WAIT_BVALID_G boolean := true
Generic

Definition at line 49 of file SrpV3Axi.vhd.

◆ AXI_STREAM_CONFIG_G

AXI_STREAM_CONFIG_G AxiStreamConfigType := ssiAxiStreamConfig ( 2 )
Generic

Definition at line 50 of file SrpV3Axi.vhd.

◆ UNALIGNED_ACCESS_G

UNALIGNED_ACCESS_G boolean := false
Generic

Definition at line 51 of file SrpV3Axi.vhd.

◆ BYTE_ACCESS_G

BYTE_ACCESS_G boolean := false
Generic

Definition at line 52 of file SrpV3Axi.vhd.

◆ WRITE_EN_G

WRITE_EN_G boolean := true
Generic

Definition at line 53 of file SrpV3Axi.vhd.

◆ READ_EN_G

READ_EN_G boolean := true
Generic

Definition at line 54 of file SrpV3Axi.vhd.

◆ sAxisClk

sAxisClk in sl
Port

Definition at line 57 of file SrpV3Axi.vhd.

◆ sAxisRst

sAxisRst in sl
Port

Definition at line 58 of file SrpV3Axi.vhd.

◆ sAxisMaster

sAxisMaster in AxiStreamMasterType
Port

Definition at line 59 of file SrpV3Axi.vhd.

◆ sAxisSlave

sAxisSlave out AxiStreamSlaveType
Port

Definition at line 60 of file SrpV3Axi.vhd.

◆ sAxisCtrl

sAxisCtrl out AxiStreamCtrlType
Port

Definition at line 61 of file SrpV3Axi.vhd.

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 63 of file SrpV3Axi.vhd.

◆ mAxisRst

mAxisRst in sl
Port

Definition at line 64 of file SrpV3Axi.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 65 of file SrpV3Axi.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType
Port

Definition at line 66 of file SrpV3Axi.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 68 of file SrpV3Axi.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 69 of file SrpV3Axi.vhd.

◆ axiWriteMaster

axiWriteMaster out AxiWriteMasterType
Port

Definition at line 70 of file SrpV3Axi.vhd.

◆ axiWriteSlave

axiWriteSlave in AxiWriteSlaveType
Port

Definition at line 71 of file SrpV3Axi.vhd.

◆ axiReadMaster

axiReadMaster out AxiReadMasterType
Port

Definition at line 72 of file SrpV3Axi.vhd.

◆ axiReadSlave

axiReadSlave in AxiReadSlaveType
Port

Definition at line 73 of file SrpV3Axi.vhd.

◆ ieee

ieee
Library

Definition at line 21 of file SrpV3Axi.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 22 of file SrpV3Axi.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 23 of file SrpV3Axi.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 24 of file SrpV3Axi.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 26 of file SrpV3Axi.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 27 of file SrpV3Axi.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 28 of file SrpV3Axi.vhd.

◆ AxiPkg

AxiPkg
Package

Definition at line 29 of file SrpV3Axi.vhd.

◆ AxiDmaPkg

AxiDmaPkg
Package

Definition at line 30 of file SrpV3Axi.vhd.

◆ SrpV3Pkg

SrpV3Pkg
Package

Definition at line 31 of file SrpV3Axi.vhd.

The documentation for this class was generated from the following file: