SURF  1.0
Generics | Ports | Libraries | Use Clauses
SrpV0AxiLite Entity Reference
protocols » srp
+ Inheritance diagram for SrpV0AxiLite:
+ Collaboration diagram for SrpV0AxiLite:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
RESP_THOLD_G  integer range 0 to ( 2 ** 24 ) := 1
SLAVE_READY_EN_G  boolean := false
EN_32BIT_ADDR_G  boolean := false
BRAM_EN_G  boolean := true
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
GEN_SYNC_FIFO_G  boolean := false
FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 9
FIFO_PAUSE_THRESH_G  integer range 1 to ( 2 ** 24 ) := 2 ** 8
AXI_STREAM_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C

Ports

sAxisClk   in sl
sAxisRst   in sl := ' 0 '
sAxisMaster   in AxiStreamMasterType
sAxisSlave   out AxiStreamSlaveType
sAxisCtrl   out AxiStreamCtrlType
mAxisClk   in sl
mAxisRst   in sl := ' 0 '
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
axiLiteClk   in sl
axiLiteRst   in sl
mAxiLiteWriteMaster   out AxiLiteWriteMasterType
mAxiLiteWriteSlave   in AxiLiteWriteSlaveType
mAxiLiteReadMaster   out AxiLiteReadMasterType
mAxiLiteReadSlave   in AxiLiteReadSlaveType

Detailed Description

See also
entity

Definition at line 35 of file SrpV0AxiLite.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 38 of file SrpV0AxiLite.vhd.

◆ RESP_THOLD_G

RESP_THOLD_G integer range 0 to ( 2 ** 24 ) := 1
Generic

Definition at line 41 of file SrpV0AxiLite.vhd.

◆ SLAVE_READY_EN_G

SLAVE_READY_EN_G boolean := false
Generic

Definition at line 42 of file SrpV0AxiLite.vhd.

◆ EN_32BIT_ADDR_G

EN_32BIT_ADDR_G boolean := false
Generic

Definition at line 43 of file SrpV0AxiLite.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 44 of file SrpV0AxiLite.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 45 of file SrpV0AxiLite.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 46 of file SrpV0AxiLite.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 47 of file SrpV0AxiLite.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 48 of file SrpV0AxiLite.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 49 of file SrpV0AxiLite.vhd.

◆ FIFO_ADDR_WIDTH_G

FIFO_ADDR_WIDTH_G integer range 4 to 48 := 9
Generic

Definition at line 50 of file SrpV0AxiLite.vhd.

◆ FIFO_PAUSE_THRESH_G

FIFO_PAUSE_THRESH_G integer range 1 to ( 2 ** 24 ) := 2 ** 8
Generic

Definition at line 51 of file SrpV0AxiLite.vhd.

◆ AXI_STREAM_CONFIG_G

AXI_STREAM_CONFIG_G AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Generic

Definition at line 54 of file SrpV0AxiLite.vhd.

◆ sAxisClk

sAxisClk in sl
Port

Definition at line 58 of file SrpV0AxiLite.vhd.

◆ sAxisRst

sAxisRst in sl := ' 0 '
Port

Definition at line 59 of file SrpV0AxiLite.vhd.

◆ sAxisMaster

sAxisMaster in AxiStreamMasterType
Port

Definition at line 60 of file SrpV0AxiLite.vhd.

◆ sAxisSlave

sAxisSlave out AxiStreamSlaveType
Port

Definition at line 61 of file SrpV0AxiLite.vhd.

◆ sAxisCtrl

sAxisCtrl out AxiStreamCtrlType
Port

Definition at line 62 of file SrpV0AxiLite.vhd.

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 65 of file SrpV0AxiLite.vhd.

◆ mAxisRst

mAxisRst in sl := ' 0 '
Port

Definition at line 66 of file SrpV0AxiLite.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 67 of file SrpV0AxiLite.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType
Port

Definition at line 68 of file SrpV0AxiLite.vhd.

◆ axiLiteClk

axiLiteClk in sl
Port

Definition at line 71 of file SrpV0AxiLite.vhd.

◆ axiLiteRst

axiLiteRst in sl
Port

Definition at line 72 of file SrpV0AxiLite.vhd.

◆ mAxiLiteWriteMaster

mAxiLiteWriteMaster out AxiLiteWriteMasterType
Port

Definition at line 73 of file SrpV0AxiLite.vhd.

◆ mAxiLiteWriteSlave

mAxiLiteWriteSlave in AxiLiteWriteSlaveType
Port

Definition at line 74 of file SrpV0AxiLite.vhd.

◆ mAxiLiteReadMaster

mAxiLiteReadMaster out AxiLiteReadMasterType
Port

Definition at line 75 of file SrpV0AxiLite.vhd.

◆ mAxiLiteReadSlave

mAxiLiteReadSlave in AxiLiteReadSlaveType
Port

Definition at line 77 of file SrpV0AxiLite.vhd.

◆ ieee

ieee
Library

Definition at line 23 of file SrpV0AxiLite.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 24 of file SrpV0AxiLite.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 25 of file SrpV0AxiLite.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 26 of file SrpV0AxiLite.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 28 of file SrpV0AxiLite.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 29 of file SrpV0AxiLite.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 30 of file SrpV0AxiLite.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 31 of file SrpV0AxiLite.vhd.

The documentation for this class was generated from the following file: