SURF  1.0
Generics | Ports | Libraries | Use Clauses
SpiMaster Entity Reference
protocols » spi
+ Inheritance diagram for SpiMaster:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
math_real 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
NUM_CHIPS_G  positive range 1 to 8 := 4
DATA_SIZE_G  natural := 16
CPHA_G  sl := ' 0 '
CPOL_G  sl := ' 0 '
CLK_PERIOD_G  real := 8 . 0E - 9
SPI_SCLK_PERIOD_G  real := 1 . 0E - 6

Ports

clk   in sl
sRst   in sl
chipSel   in slv ( log2 ( NUM_CHIPS_G ) - 1 downto 0 )
wrEn   in sl
wrData   in slv ( DATA_SIZE_G - 1 downto 0 )
dataSize   in slv ( log2 ( DATA_SIZE_G ) - 1 downto 0 ) := toSlv ( DATA_SIZE_G - 1 , log2 ( DATA_SIZE_G ) )
rdEn   out sl
rdData   out slv ( DATA_SIZE_G - 1 downto 0 )
shiftCount   out slv ( bitSize ( DATA_SIZE_G ) - 1 downto 0 )
spiCsL   out slv ( NUM_CHIPS_G - 1 downto 0 )
spiSclk   out sl
spiSdi   out sl
spiSdo   in sl

Detailed Description

See also
entity

Definition at line 27 of file SpiMaster.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file SpiMaster.vhd.

◆ NUM_CHIPS_G

NUM_CHIPS_G positive range 1 to 8 := 4
Generic

Definition at line 30 of file SpiMaster.vhd.

◆ DATA_SIZE_G

DATA_SIZE_G natural := 16
Generic

Definition at line 31 of file SpiMaster.vhd.

◆ CPHA_G

CPHA_G sl := ' 0 '
Generic

Definition at line 32 of file SpiMaster.vhd.

◆ CPOL_G

CPOL_G sl := ' 0 '
Generic

Definition at line 33 of file SpiMaster.vhd.

◆ CLK_PERIOD_G

CLK_PERIOD_G real := 8 . 0E - 9
Generic

Definition at line 34 of file SpiMaster.vhd.

◆ SPI_SCLK_PERIOD_G

SPI_SCLK_PERIOD_G real := 1 . 0E - 6
Generic

Definition at line 35 of file SpiMaster.vhd.

◆ clk

clk in sl
Port

Definition at line 38 of file SpiMaster.vhd.

◆ sRst

sRst in sl
Port

Definition at line 39 of file SpiMaster.vhd.

◆ chipSel

chipSel in slv ( log2 ( NUM_CHIPS_G ) - 1 downto 0 )
Port

Definition at line 41 of file SpiMaster.vhd.

◆ wrEn

wrEn in sl
Port

Definition at line 42 of file SpiMaster.vhd.

◆ wrData

wrData in slv ( DATA_SIZE_G - 1 downto 0 )
Port

Definition at line 43 of file SpiMaster.vhd.

◆ dataSize

dataSize in slv ( log2 ( DATA_SIZE_G ) - 1 downto 0 ) := toSlv ( DATA_SIZE_G - 1 , log2 ( DATA_SIZE_G ) )
Port

Definition at line 44 of file SpiMaster.vhd.

◆ rdEn

rdEn out sl
Port

Definition at line 45 of file SpiMaster.vhd.

◆ rdData

rdData out slv ( DATA_SIZE_G - 1 downto 0 )
Port

Definition at line 46 of file SpiMaster.vhd.

◆ shiftCount

shiftCount out slv ( bitSize ( DATA_SIZE_G ) - 1 downto 0 )
Port

Definition at line 47 of file SpiMaster.vhd.

◆ spiCsL

spiCsL out slv ( NUM_CHIPS_G - 1 downto 0 )
Port

Definition at line 49 of file SpiMaster.vhd.

◆ spiSclk

spiSclk out sl
Port

Definition at line 50 of file SpiMaster.vhd.

◆ spiSdi

spiSdi out sl
Port

Definition at line 51 of file SpiMaster.vhd.

◆ spiSdo

spiSdo in sl
Port

Definition at line 52 of file SpiMaster.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file SpiMaster.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file SpiMaster.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file SpiMaster.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file SpiMaster.vhd.

◆ math_real

math_real
Package

Definition at line 22 of file SpiMaster.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file SpiMaster.vhd.

The documentation for this class was generated from the following file: