SURF  1.0
Generics | Ports | Libraries | Use Clauses
SaciPrepRdout Entity Reference
protocols » saci

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
MASK_REG_ADDR_G  slv ( 31 downto 0 ) := x " 00000034 "
SACI_BASE_ADDR_G  slv ( 31 downto 0 ) := x " 02000000 "
AXIL_ERR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
SACI_NUM_CHIPS_G  natural range 1 to 4 := 4

Ports

axilClk   in sl
axilRst   in sl
prepRdoutReq   in sl
prepRdoutAck   out sl
sAxilWriteMaster   in AxiLiteWriteMasterType
sAxilWriteSlave   out AxiLiteWriteSlaveType
sAxilReadMaster   in AxiLiteReadMasterType
sAxilReadSlave   out AxiLiteReadSlaveType
mAxilWriteMaster   out AxiLiteWriteMasterType
mAxilWriteSlave   in AxiLiteWriteSlaveType
mAxilReadMaster   out AxiLiteReadMasterType
mAxilReadSlave   in AxiLiteReadSlaveType

Detailed Description

See also
entity

Definition at line 28 of file SaciPrepRdout.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file SaciPrepRdout.vhd.

◆ MASK_REG_ADDR_G

MASK_REG_ADDR_G slv ( 31 downto 0 ) := x " 00000034 "
Generic

Definition at line 31 of file SaciPrepRdout.vhd.

◆ SACI_BASE_ADDR_G

SACI_BASE_ADDR_G slv ( 31 downto 0 ) := x " 02000000 "
Generic

Definition at line 32 of file SaciPrepRdout.vhd.

◆ AXIL_ERR_RESP_G

AXIL_ERR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 33 of file SaciPrepRdout.vhd.

◆ SACI_NUM_CHIPS_G

SACI_NUM_CHIPS_G natural range 1 to 4 := 4
Generic

Definition at line 35 of file SaciPrepRdout.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 37 of file SaciPrepRdout.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 38 of file SaciPrepRdout.vhd.

◆ prepRdoutReq

prepRdoutReq in sl
Port

Definition at line 41 of file SaciPrepRdout.vhd.

◆ prepRdoutAck

prepRdoutAck out sl
Port

Definition at line 42 of file SaciPrepRdout.vhd.

◆ sAxilWriteMaster

sAxilWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 45 of file SaciPrepRdout.vhd.

◆ sAxilWriteSlave

sAxilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 46 of file SaciPrepRdout.vhd.

◆ sAxilReadMaster

sAxilReadMaster in AxiLiteReadMasterType
Port

Definition at line 47 of file SaciPrepRdout.vhd.

◆ sAxilReadSlave

sAxilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 48 of file SaciPrepRdout.vhd.

◆ mAxilWriteMaster

mAxilWriteMaster out AxiLiteWriteMasterType
Port

Definition at line 51 of file SaciPrepRdout.vhd.

◆ mAxilWriteSlave

mAxilWriteSlave in AxiLiteWriteSlaveType
Port

Definition at line 52 of file SaciPrepRdout.vhd.

◆ mAxilReadMaster

mAxilReadMaster out AxiLiteReadMasterType
Port

Definition at line 53 of file SaciPrepRdout.vhd.

◆ mAxilReadSlave

mAxilReadSlave in AxiLiteReadSlaveType
Port

Definition at line 55 of file SaciPrepRdout.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file SaciPrepRdout.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file SaciPrepRdout.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file SaciPrepRdout.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file SaciPrepRdout.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file SaciPrepRdout.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file SaciPrepRdout.vhd.

The documentation for this class was generated from the following file: