SURF  1.0
Generics | Ports | Libraries | Use Clauses
RssiCore Entity Reference
protocols » rssi
+ Inheritance diagram for RssiCore:
+ Collaboration diagram for RssiCore:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
math_real 
StdRtlPkg  Package <StdRtlPkg>
RssiPkg  Package <RssiPkg>
SsiPkg  Package <SsiPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
CLK_FREQUENCY_G  real := 100 . 0E6
TIMEOUT_UNIT_G  real := 1 . 0E - 6
SERVER_G  boolean := true
RETRANSMIT_ENABLE_G  boolean := true
WINDOW_ADDR_SIZE_G  positive range 1 to 10 := 3
SEGMENT_ADDR_SIZE_G  positive := 7
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
APP_AXIS_CONFIG_G  AxiStreamConfigType := ssiAxiStreamConfig ( 4 , TKEEP_NORMAL_C )
TSP_AXIS_CONFIG_G  AxiStreamConfigType := ssiAxiStreamConfig ( 16 , TKEEP_NORMAL_C )
INIT_SEQ_N_G  natural := 16#80#
CONN_ID_G  positive := 16#12345678#
VERSION_G  positive := 1
HEADER_CHKSUM_EN_G  boolean := true
MAX_NUM_OUTS_SEG_G  positive range 2 to 1024 := 8
MAX_SEG_SIZE_G  positive := 1024
ACK_TOUT_G  positive := 25
RETRANS_TOUT_G  positive := 50
NULL_TOUT_G  positive := 200
MAX_RETRANS_CNT_G  positive := 2
MAX_CUM_ACK_CNT_G  positive := 3

Ports

clk_i   in sl
rst_i   in sl
openRq_i   in sl
closeRq_i   in sl
inject_i   in sl := ' 0 '
sAppAxisMaster_i   in AxiStreamMasterType
sAppAxisSlave_o   out AxiStreamSlaveType
mAppAxisMaster_o   out AxiStreamMasterType
mAppAxisSlave_i   in AxiStreamSlaveType
sTspAxisMaster_i   in AxiStreamMasterType
sTspAxisSlave_o   out AxiStreamSlaveType
mTspAxisMaster_o   out AxiStreamMasterType
mTspAxisSlave_i   in AxiStreamSlaveType
axiClk_i   in sl := ' 0 '
axiRst_i   in sl := ' 0 '
axilReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out AxiLiteWriteSlaveType
statusReg_o   out slv ( 6 downto 0 )

Detailed Description

See also
entity

Definition at line 51 of file RssiCore.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 53 of file RssiCore.vhd.

◆ CLK_FREQUENCY_G

CLK_FREQUENCY_G real := 100 . 0E6
Generic

Definition at line 54 of file RssiCore.vhd.

◆ TIMEOUT_UNIT_G

TIMEOUT_UNIT_G real := 1 . 0E - 6
Generic

Definition at line 55 of file RssiCore.vhd.

◆ SERVER_G

SERVER_G boolean := true
Generic

Definition at line 57 of file RssiCore.vhd.

◆ RETRANSMIT_ENABLE_G

RETRANSMIT_ENABLE_G boolean := true
Generic

Definition at line 59 of file RssiCore.vhd.

◆ WINDOW_ADDR_SIZE_G

WINDOW_ADDR_SIZE_G positive range 1 to 10 := 3
Generic

Definition at line 61 of file RssiCore.vhd.

◆ SEGMENT_ADDR_SIZE_G

SEGMENT_ADDR_SIZE_G positive := 7
Generic

Definition at line 62 of file RssiCore.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 64 of file RssiCore.vhd.

◆ APP_AXIS_CONFIG_G

APP_AXIS_CONFIG_G AxiStreamConfigType := ssiAxiStreamConfig ( 4 , TKEEP_NORMAL_C )
Generic

Definition at line 67 of file RssiCore.vhd.

◆ TSP_AXIS_CONFIG_G

TSP_AXIS_CONFIG_G AxiStreamConfigType := ssiAxiStreamConfig ( 16 , TKEEP_NORMAL_C )
Generic

Definition at line 68 of file RssiCore.vhd.

◆ INIT_SEQ_N_G

INIT_SEQ_N_G natural := 16#80#
Generic

Definition at line 73 of file RssiCore.vhd.

◆ CONN_ID_G

CONN_ID_G positive := 16#12345678#
Generic

Definition at line 74 of file RssiCore.vhd.

◆ VERSION_G

VERSION_G positive := 1
Generic

Definition at line 75 of file RssiCore.vhd.

◆ HEADER_CHKSUM_EN_G

HEADER_CHKSUM_EN_G boolean := true
Generic

Definition at line 76 of file RssiCore.vhd.

◆ MAX_NUM_OUTS_SEG_G

MAX_NUM_OUTS_SEG_G positive range 2 to 1024 := 8
Generic

Definition at line 79 of file RssiCore.vhd.

◆ MAX_SEG_SIZE_G

MAX_SEG_SIZE_G positive := 1024
Generic

Definition at line 80 of file RssiCore.vhd.

◆ ACK_TOUT_G

ACK_TOUT_G positive := 25
Generic

Definition at line 83 of file RssiCore.vhd.

◆ RETRANS_TOUT_G

RETRANS_TOUT_G positive := 50
Generic

Definition at line 84 of file RssiCore.vhd.

◆ NULL_TOUT_G

NULL_TOUT_G positive := 200
Generic

Definition at line 85 of file RssiCore.vhd.

◆ MAX_RETRANS_CNT_G

MAX_RETRANS_CNT_G positive := 2
Generic

Definition at line 88 of file RssiCore.vhd.

◆ MAX_CUM_ACK_CNT_G

MAX_CUM_ACK_CNT_G positive := 3
Generic

Definition at line 90 of file RssiCore.vhd.

◆ clk_i

clk_i in sl
Port

Definition at line 92 of file RssiCore.vhd.

◆ rst_i

rst_i in sl
Port

Definition at line 93 of file RssiCore.vhd.

◆ openRq_i

openRq_i in sl
Port

Definition at line 96 of file RssiCore.vhd.

◆ closeRq_i

closeRq_i in sl
Port

Definition at line 97 of file RssiCore.vhd.

◆ inject_i

inject_i in sl := ' 0 '
Port

Definition at line 98 of file RssiCore.vhd.

◆ sAppAxisMaster_i

sAppAxisMaster_i in AxiStreamMasterType
Port

Definition at line 101 of file RssiCore.vhd.

◆ sAppAxisSlave_o

sAppAxisSlave_o out AxiStreamSlaveType
Port

Definition at line 102 of file RssiCore.vhd.

◆ mAppAxisMaster_o

mAppAxisMaster_o out AxiStreamMasterType
Port

Definition at line 103 of file RssiCore.vhd.

◆ mAppAxisSlave_i

mAppAxisSlave_i in AxiStreamSlaveType
Port

Definition at line 104 of file RssiCore.vhd.

◆ sTspAxisMaster_i

sTspAxisMaster_i in AxiStreamMasterType
Port

Definition at line 107 of file RssiCore.vhd.

◆ sTspAxisSlave_o

sTspAxisSlave_o out AxiStreamSlaveType
Port

Definition at line 108 of file RssiCore.vhd.

◆ mTspAxisMaster_o

mTspAxisMaster_o out AxiStreamMasterType
Port

Definition at line 109 of file RssiCore.vhd.

◆ mTspAxisSlave_i

mTspAxisSlave_i in AxiStreamSlaveType
Port

Definition at line 110 of file RssiCore.vhd.

◆ axiClk_i

axiClk_i in sl := ' 0 '
Port

Definition at line 113 of file RssiCore.vhd.

◆ axiRst_i

axiRst_i in sl := ' 0 '
Port

Definition at line 114 of file RssiCore.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 115 of file RssiCore.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 116 of file RssiCore.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 117 of file RssiCore.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 118 of file RssiCore.vhd.

◆ statusReg_o

statusReg_o out slv ( 6 downto 0 )
Port

Definition at line 121 of file RssiCore.vhd.

◆ ieee

ieee
Library

Definition at line 37 of file RssiCore.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 38 of file RssiCore.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 39 of file RssiCore.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 40 of file RssiCore.vhd.

◆ math_real

math_real
Package

Definition at line 41 of file RssiCore.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 43 of file RssiCore.vhd.

◆ RssiPkg

RssiPkg
Package

Definition at line 44 of file RssiCore.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 45 of file RssiCore.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 46 of file RssiCore.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 47 of file RssiCore.vhd.

The documentation for this class was generated from the following file: