SURF  1.0
Generics | Ports | Libraries | Use Clauses
RegisterVector Entity Reference
base » general

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
RST_POLARITY_G  sl := ' 1 '
WIDTH_G  positive := 1
INIT_G  slv := " 0 "

Ports

clk   in sl
rst   in sl := not RST_POLARITY_G
en   in sl := ' 1 '
sig_i   in slv ( WIDTH_G - 1 downto 0 )
reg_o   out slv ( WIDTH_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 27 of file RegisterVector.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 29 of file RegisterVector.vhd.

◆ RST_POLARITY_G

RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 30 of file RegisterVector.vhd.

◆ WIDTH_G

WIDTH_G positive := 1
Generic

Definition at line 31 of file RegisterVector.vhd.

◆ INIT_G

INIT_G slv := " 0 "
Generic

Definition at line 32 of file RegisterVector.vhd.

◆ clk

clk in sl
Port

Definition at line 34 of file RegisterVector.vhd.

◆ rst

rst in sl := not RST_POLARITY_G
Port

Definition at line 35 of file RegisterVector.vhd.

◆ en

en in sl := ' 1 '
Port

Definition at line 36 of file RegisterVector.vhd.

◆ sig_i

sig_i in slv ( WIDTH_G - 1 downto 0 )
Port

Definition at line 37 of file RegisterVector.vhd.

◆ reg_o

reg_o out slv ( WIDTH_G - 1 downto 0 )
Port

Definition at line 38 of file RegisterVector.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file RegisterVector.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file RegisterVector.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file RegisterVector.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file RegisterVector.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file RegisterVector.vhd.

The documentation for this class was generated from the following file: