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Pgp2bGtx7Fixedlat Entity Reference
protocols » pgp » pgp2b » gtx7
+ Inheritance diagram for Pgp2bGtx7Fixedlat:
+ Collaboration diagram for Pgp2bGtx7Fixedlat:

Entities

rtl  architecture
 

Libraries

ieee 
UNISIM 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
Pgp2bPkg  Package <Pgp2bPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
VCOMPONENTS 

Generics

TPD_G  time := 1 ns
SIM_GTRESET_SPEEDUP_G  string := " FALSE "
SIM_VERSION_G  string := " 4.0 "
SIMULATION_G  boolean := false
STABLE_CLOCK_PERIOD_G  real := 8 . 0E - 9
CPLL_REFCLK_SEL_G  bit_vector := " 001 "
CPLL_FBDIV_G  integer := 4
CPLL_FBDIV_45_G  integer := 5
CPLL_REFCLK_DIV_G  integer := 1
RXOUT_DIV_G  integer := 2
TXOUT_DIV_G  integer := 2
RX_CLK25_DIV_G  integer := 5
TX_CLK25_DIV_G  integer := 5
PMA_RSV_G  bit_vector := x " 00018480 "
RX_OS_CFG_G  bit_vector := " 0000010000000 "
RXCDR_CFG_G  bit_vector := x " 03000023ff40200020 "
RXDFEXYDEN_G  sl := ' 0 '
RX_DFE_KL_CFG2_G  bit_vector := x " 3008E56A "
TX_BUF_EN_G  boolean := false
TX_OUTCLK_SRC_G  string := " PLLREFCLK "
TX_PHASE_ALIGN_G  string := " MANUAL "
TX_PLL_G  string := " QPLL "
RX_PLL_G  string := " CPLL "
VC_INTERLEAVE_G  integer := 0
PAYLOAD_CNT_TOP_G  integer := 7
NUM_VC_EN_G  integer range 1 to 4 := 4
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
TX_ENABLE_G  boolean := true
RX_ENABLE_G  boolean := true

Ports

stableClk   in sl
gtCPllRefClk   in sl := ' 0 '
gtCPllLock   out sl
gtQPllRefClk   in sl := ' 0 '
gtQPllClk   in sl := ' 0 '
gtQPllLock   in sl := ' 0 '
gtQPllRefClkLost   in sl := ' 0 '
gtQPllReset   out sl
gtRxRefClkBufg   in sl
gtTxOutClk   out sl
gtRxN   in sl
gtRxP   in sl
gtTxN   out sl
gtTxP   out sl
pgpTxReset   in sl
pgpTxClk   in sl
pgpRxReset   in sl
pgpRxRecClk   out sl
pgpRxRecClkRst   out sl
pgpRxClk   in sl
pgpRxMmcmReset   out sl
pgpRxMmcmLocked   in sl := ' 1 '
pgpRxIn   in Pgp2bRxInType
pgpRxOut   out Pgp2bRxOutType
pgpTxIn   in Pgp2bTxInType
pgpTxOut   out Pgp2bTxOutType
pgpTxMasters   in AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpTxSlaves   out AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters   out AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed   out AxiStreamMasterType
pgpRxCtrl   in AxiStreamCtrlArray ( 3 downto 0 )
txPreCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor   in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl   in slv ( 3 downto 0 ) := " 1000 "
axilClk   in sl := ' 0 '
axilRst   in sl := ' 0 '
axilReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 31 of file Pgp2bGtx7FixedLat.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file Pgp2bGtx7FixedLat.vhd.

◆ SIM_GTRESET_SPEEDUP_G

SIM_GTRESET_SPEEDUP_G string := " FALSE "
Generic

Definition at line 39 of file Pgp2bGtx7FixedLat.vhd.

◆ SIM_VERSION_G

SIM_VERSION_G string := " 4.0 "
Generic

Definition at line 40 of file Pgp2bGtx7FixedLat.vhd.

◆ SIMULATION_G

SIMULATION_G boolean := false
Generic

Definition at line 41 of file Pgp2bGtx7FixedLat.vhd.

◆ STABLE_CLOCK_PERIOD_G

STABLE_CLOCK_PERIOD_G real := 8 . 0E - 9
Generic

Definition at line 42 of file Pgp2bGtx7FixedLat.vhd.

◆ CPLL_REFCLK_SEL_G

CPLL_REFCLK_SEL_G bit_vector := " 001 "
Generic

Definition at line 44 of file Pgp2bGtx7FixedLat.vhd.

◆ CPLL_FBDIV_G

CPLL_FBDIV_G integer := 4
Generic

Definition at line 45 of file Pgp2bGtx7FixedLat.vhd.

◆ CPLL_FBDIV_45_G

CPLL_FBDIV_45_G integer := 5
Generic

Definition at line 46 of file Pgp2bGtx7FixedLat.vhd.

◆ CPLL_REFCLK_DIV_G

CPLL_REFCLK_DIV_G integer := 1
Generic

Definition at line 47 of file Pgp2bGtx7FixedLat.vhd.

◆ RXOUT_DIV_G

RXOUT_DIV_G integer := 2
Generic

Definition at line 48 of file Pgp2bGtx7FixedLat.vhd.

◆ TXOUT_DIV_G

TXOUT_DIV_G integer := 2
Generic

Definition at line 49 of file Pgp2bGtx7FixedLat.vhd.

◆ RX_CLK25_DIV_G

RX_CLK25_DIV_G integer := 5
Generic

Definition at line 50 of file Pgp2bGtx7FixedLat.vhd.

◆ TX_CLK25_DIV_G

TX_CLK25_DIV_G integer := 5
Generic

Definition at line 51 of file Pgp2bGtx7FixedLat.vhd.

◆ PMA_RSV_G

PMA_RSV_G bit_vector := x " 00018480 "
Generic

Definition at line 53 of file Pgp2bGtx7FixedLat.vhd.

◆ RX_OS_CFG_G

RX_OS_CFG_G bit_vector := " 0000010000000 "
Generic

Definition at line 54 of file Pgp2bGtx7FixedLat.vhd.

◆ RXCDR_CFG_G

RXCDR_CFG_G bit_vector := x " 03000023ff40200020 "
Generic

Definition at line 55 of file Pgp2bGtx7FixedLat.vhd.

◆ RXDFEXYDEN_G

RXDFEXYDEN_G sl := ' 0 '
Generic

Definition at line 56 of file Pgp2bGtx7FixedLat.vhd.

◆ RX_DFE_KL_CFG2_G

RX_DFE_KL_CFG2_G bit_vector := x " 3008E56A "
Generic

Definition at line 57 of file Pgp2bGtx7FixedLat.vhd.

◆ TX_BUF_EN_G

TX_BUF_EN_G boolean := false
Generic

Definition at line 59 of file Pgp2bGtx7FixedLat.vhd.

◆ TX_OUTCLK_SRC_G

TX_OUTCLK_SRC_G string := " PLLREFCLK "
Generic

Definition at line 60 of file Pgp2bGtx7FixedLat.vhd.

◆ TX_PHASE_ALIGN_G

TX_PHASE_ALIGN_G string := " MANUAL "
Generic

Definition at line 61 of file Pgp2bGtx7FixedLat.vhd.

◆ TX_PLL_G

TX_PLL_G string := " QPLL "
Generic

Definition at line 63 of file Pgp2bGtx7FixedLat.vhd.

◆ RX_PLL_G

RX_PLL_G string := " CPLL "
Generic

Definition at line 64 of file Pgp2bGtx7FixedLat.vhd.

◆ VC_INTERLEAVE_G

VC_INTERLEAVE_G integer := 0
Generic

Definition at line 69 of file Pgp2bGtx7FixedLat.vhd.

◆ PAYLOAD_CNT_TOP_G

PAYLOAD_CNT_TOP_G integer := 7
Generic

Definition at line 70 of file Pgp2bGtx7FixedLat.vhd.

◆ NUM_VC_EN_G

NUM_VC_EN_G integer range 1 to 4 := 4
Generic

Definition at line 71 of file Pgp2bGtx7FixedLat.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 72 of file Pgp2bGtx7FixedLat.vhd.

◆ TX_ENABLE_G

TX_ENABLE_G boolean := true
Generic

Definition at line 73 of file Pgp2bGtx7FixedLat.vhd.

◆ RX_ENABLE_G

RX_ENABLE_G boolean := true
Generic

Definition at line 74 of file Pgp2bGtx7FixedLat.vhd.

◆ stableClk

stableClk in sl
Port

Definition at line 77 of file Pgp2bGtx7FixedLat.vhd.

◆ gtCPllRefClk

gtCPllRefClk in sl := ' 0 '
Port

Definition at line 78 of file Pgp2bGtx7FixedLat.vhd.

◆ gtCPllLock

gtCPllLock out sl
Port

Definition at line 79 of file Pgp2bGtx7FixedLat.vhd.

◆ gtQPllRefClk

gtQPllRefClk in sl := ' 0 '
Port

Definition at line 80 of file Pgp2bGtx7FixedLat.vhd.

◆ gtQPllClk

gtQPllClk in sl := ' 0 '
Port

Definition at line 81 of file Pgp2bGtx7FixedLat.vhd.

◆ gtQPllLock

gtQPllLock in sl := ' 0 '
Port

Definition at line 82 of file Pgp2bGtx7FixedLat.vhd.

◆ gtQPllRefClkLost

gtQPllRefClkLost in sl := ' 0 '
Port

Definition at line 83 of file Pgp2bGtx7FixedLat.vhd.

◆ gtQPllReset

gtQPllReset out sl
Port

Definition at line 84 of file Pgp2bGtx7FixedLat.vhd.

◆ gtRxRefClkBufg

gtRxRefClkBufg in sl
Port

Definition at line 85 of file Pgp2bGtx7FixedLat.vhd.

◆ gtTxOutClk

gtTxOutClk out sl
Port

Definition at line 86 of file Pgp2bGtx7FixedLat.vhd.

◆ gtRxN

gtRxN in sl
Port

Definition at line 89 of file Pgp2bGtx7FixedLat.vhd.

◆ gtRxP

gtRxP in sl
Port

Definition at line 90 of file Pgp2bGtx7FixedLat.vhd.

◆ gtTxN

gtTxN out sl
Port

Definition at line 91 of file Pgp2bGtx7FixedLat.vhd.

◆ gtTxP

gtTxP out sl
Port

Definition at line 92 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpTxReset

pgpTxReset in sl
Port

Definition at line 95 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpTxClk

pgpTxClk in sl
Port

Definition at line 96 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxReset

pgpRxReset in sl
Port

Definition at line 99 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxRecClk

pgpRxRecClk out sl
Port

Definition at line 100 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxRecClkRst

pgpRxRecClkRst out sl
Port

Definition at line 101 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxClk

pgpRxClk in sl
Port

Definition at line 102 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxMmcmReset

pgpRxMmcmReset out sl
Port

Definition at line 103 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxMmcmLocked

pgpRxMmcmLocked in sl := ' 1 '
Port

Definition at line 104 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxIn

pgpRxIn in Pgp2bRxInType
Port

Definition at line 107 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxOut

pgpRxOut out Pgp2bRxOutType
Port

Definition at line 108 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpTxIn

pgpTxIn in Pgp2bTxInType
Port

Definition at line 111 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpTxOut

pgpTxOut out Pgp2bTxOutType
Port

Definition at line 112 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpTxMasters

pgpTxMasters in AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
Port

Definition at line 115 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpTxSlaves

pgpTxSlaves out AxiStreamSlaveArray ( 3 downto 0 )
Port

Definition at line 116 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxMasters

pgpRxMasters out AxiStreamMasterArray ( 3 downto 0 )
Port

Definition at line 119 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxMasterMuxed

pgpRxMasterMuxed out AxiStreamMasterType
Port

Definition at line 120 of file Pgp2bGtx7FixedLat.vhd.

◆ pgpRxCtrl

pgpRxCtrl in AxiStreamCtrlArray ( 3 downto 0 )
Port

Definition at line 121 of file Pgp2bGtx7FixedLat.vhd.

◆ txPreCursor

txPreCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 124 of file Pgp2bGtx7FixedLat.vhd.

◆ txPostCursor

txPostCursor in slv ( 4 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 125 of file Pgp2bGtx7FixedLat.vhd.

◆ txDiffCtrl

txDiffCtrl in slv ( 3 downto 0 ) := " 1000 "
Port

Definition at line 126 of file Pgp2bGtx7FixedLat.vhd.

◆ axilClk

axilClk in sl := ' 0 '
Port

Definition at line 128 of file Pgp2bGtx7FixedLat.vhd.

◆ axilRst

axilRst in sl := ' 0 '
Port

Definition at line 129 of file Pgp2bGtx7FixedLat.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 130 of file Pgp2bGtx7FixedLat.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 131 of file Pgp2bGtx7FixedLat.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 132 of file Pgp2bGtx7FixedLat.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 133 of file Pgp2bGtx7FixedLat.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file Pgp2bGtx7FixedLat.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file Pgp2bGtx7FixedLat.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file Pgp2bGtx7FixedLat.vhd.

◆ Pgp2bPkg

Pgp2bPkg
Package

Definition at line 22 of file Pgp2bGtx7FixedLat.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 23 of file Pgp2bGtx7FixedLat.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file Pgp2bGtx7FixedLat.vhd.

◆ UNISIM

UNISIM
Library

Definition at line 26 of file Pgp2bGtx7FixedLat.vhd.

◆ VCOMPONENTS

VCOMPONENTS
Package

Definition at line 27 of file Pgp2bGtx7FixedLat.vhd.

The documentation for this class was generated from the following file: