SURF  1.0
Generics | Ports | Libraries | Use Clauses
MicroblazeBasicCoreWrapper Entity Reference
+ Inheritance diagram for MicroblazeBasicCoreWrapper:
+ Collaboration diagram for MicroblazeBasicCoreWrapper:

Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
SsiPkg  Package <SsiPkg>

Generics

TPD_G  time := 1 ns
AXIL_RESP_C  boolean := false
AXIL_ADDR_MSB_C  boolean := false

Ports

mAxilWriteMaster   out AxiLiteWriteMasterType
mAxilWriteSlave   in AxiLiteWriteSlaveType
mAxilReadMaster   out AxiLiteReadMasterType
mAxilReadSlave   in AxiLiteReadSlaveType
sAxisMaster   in AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave   out AxiStreamSlaveType
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
interrupt   in slv ( 7 downto 0 ) := ( others = > ' 0 ' )
clk   in sl
pllLock   in sl := ' 1 '
rst   in sl

Detailed Description

Definition at line 26 of file MicroblazeBasicCoreWrapper.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 28 of file MicroblazeBasicCoreWrapper.vhd.

◆ AXIL_RESP_C

AXIL_RESP_C boolean := false
Generic

Definition at line 29 of file MicroblazeBasicCoreWrapper.vhd.

◆ AXIL_ADDR_MSB_C

AXIL_ADDR_MSB_C boolean := false
Generic

Definition at line 30 of file MicroblazeBasicCoreWrapper.vhd.

◆ mAxilWriteMaster

mAxilWriteMaster out AxiLiteWriteMasterType
Port

Definition at line 33 of file MicroblazeBasicCoreWrapper.vhd.

◆ mAxilWriteSlave

mAxilWriteSlave in AxiLiteWriteSlaveType
Port

Definition at line 34 of file MicroblazeBasicCoreWrapper.vhd.

◆ mAxilReadMaster

mAxilReadMaster out AxiLiteReadMasterType
Port

Definition at line 35 of file MicroblazeBasicCoreWrapper.vhd.

◆ mAxilReadSlave

mAxilReadSlave in AxiLiteReadSlaveType
Port

Definition at line 36 of file MicroblazeBasicCoreWrapper.vhd.

◆ sAxisMaster

sAxisMaster in AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
Port

Definition at line 38 of file MicroblazeBasicCoreWrapper.vhd.

◆ sAxisSlave

sAxisSlave out AxiStreamSlaveType
Port

Definition at line 39 of file MicroblazeBasicCoreWrapper.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 41 of file MicroblazeBasicCoreWrapper.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
Port

Definition at line 42 of file MicroblazeBasicCoreWrapper.vhd.

◆ interrupt

interrupt in slv ( 7 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 44 of file MicroblazeBasicCoreWrapper.vhd.

◆ clk

clk in sl
Port

Definition at line 46 of file MicroblazeBasicCoreWrapper.vhd.

◆ pllLock

pllLock in sl := ' 1 '
Port

Definition at line 47 of file MicroblazeBasicCoreWrapper.vhd.

◆ rst

rst in sl
Port

Definition at line 48 of file MicroblazeBasicCoreWrapper.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file MicroblazeBasicCoreWrapper.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file MicroblazeBasicCoreWrapper.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file MicroblazeBasicCoreWrapper.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 22 of file MicroblazeBasicCoreWrapper.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 23 of file MicroblazeBasicCoreWrapper.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 24 of file MicroblazeBasicCoreWrapper.vhd.

The documentation for this class was generated from the following file: