SURF  1.0
Generics | Ports | Libraries | Use Clauses
JesdTxReg Entity Reference
protocols » jesd204b
+ Inheritance diagram for JesdTxReg:
+ Collaboration diagram for JesdTxReg:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
Jesd204bPkg  Package <Jesd204bPkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
L_G  positive range 1 to 16 := 2
F_G  positive := 2

Ports

axiClk_i   in sl
axiRst_i   in sl
axilReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out AxiLiteWriteSlaveType
devClk_i   in sl
devRst_i   in sl
statusTxArr_i   in txStatuRegisterArray ( L_G - 1 downto 0 )
muxOutSelArr_o   out Slv3Array ( L_G - 1 downto 0 )
sigTypeArr_o   out Slv2Array ( L_G - 1 downto 0 )
sysrefDlyTx_o   out slv ( SYSRF_DLY_WIDTH_C - 1 downto 0 )
enableTx_o   out slv ( L_G - 1 downto 0 )
replEnable_o   out sl
scrEnable_o   out sl
invertData_o   out slv ( L_G - 1 downto 0 )
rampStep_o   out slv ( PER_STEP_WIDTH_C - 1 downto 0 )
squarePeriod_o   out slv ( PER_STEP_WIDTH_C - 1 downto 0 )
subClass_o   out sl
gtReset_o   out sl
clearErr_o   out sl
invertSync_o   out sl
enableTestSig_o   out sl
posAmplitude_o   out slv ( F_G * 8 - 1 downto 0 )
negAmplitude_o   out slv ( F_G * 8 - 1 downto 0 )
txDiffCtrl   out Slv8Array ( L_G - 1 downto 0 )
txPostCursor   out Slv8Array ( L_G - 1 downto 0 )
txPreCursor   out Slv8Array ( L_G - 1 downto 0 )
txPolarity   out slv ( L_G - 1 downto 0 )
loopback   out slv ( L_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 29 of file JesdTxReg.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file JesdTxReg.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 33 of file JesdTxReg.vhd.

◆ L_G

L_G positive range 1 to 16 := 2
Generic

Definition at line 35 of file JesdTxReg.vhd.

◆ F_G

F_G positive := 2
Generic

Definition at line 36 of file JesdTxReg.vhd.

◆ axiClk_i

axiClk_i in sl
Port

Definition at line 39 of file JesdTxReg.vhd.

◆ axiRst_i

axiRst_i in sl
Port

Definition at line 40 of file JesdTxReg.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 43 of file JesdTxReg.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 44 of file JesdTxReg.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 45 of file JesdTxReg.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 46 of file JesdTxReg.vhd.

◆ devClk_i

devClk_i in sl
Port

Definition at line 49 of file JesdTxReg.vhd.

◆ devRst_i

devRst_i in sl
Port

Definition at line 50 of file JesdTxReg.vhd.

◆ statusTxArr_i

statusTxArr_i in txStatuRegisterArray ( L_G - 1 downto 0 )
Port

Definition at line 54 of file JesdTxReg.vhd.

◆ muxOutSelArr_o

muxOutSelArr_o out Slv3Array ( L_G - 1 downto 0 )
Port

Definition at line 57 of file JesdTxReg.vhd.

◆ sigTypeArr_o

sigTypeArr_o out Slv2Array ( L_G - 1 downto 0 )
Port

Definition at line 58 of file JesdTxReg.vhd.

◆ sysrefDlyTx_o

sysrefDlyTx_o out slv ( SYSRF_DLY_WIDTH_C - 1 downto 0 )
Port

Definition at line 59 of file JesdTxReg.vhd.

◆ enableTx_o

enableTx_o out slv ( L_G - 1 downto 0 )
Port

Definition at line 60 of file JesdTxReg.vhd.

◆ replEnable_o

replEnable_o out sl
Port

Definition at line 61 of file JesdTxReg.vhd.

◆ scrEnable_o

scrEnable_o out sl
Port

Definition at line 62 of file JesdTxReg.vhd.

◆ invertData_o

invertData_o out slv ( L_G - 1 downto 0 )
Port

Definition at line 63 of file JesdTxReg.vhd.

◆ rampStep_o

rampStep_o out slv ( PER_STEP_WIDTH_C - 1 downto 0 )
Port

Definition at line 64 of file JesdTxReg.vhd.

◆ squarePeriod_o

squarePeriod_o out slv ( PER_STEP_WIDTH_C - 1 downto 0 )
Port

Definition at line 65 of file JesdTxReg.vhd.

◆ subClass_o

subClass_o out sl
Port

Definition at line 66 of file JesdTxReg.vhd.

◆ gtReset_o

gtReset_o out sl
Port

Definition at line 67 of file JesdTxReg.vhd.

◆ clearErr_o

clearErr_o out sl
Port

Definition at line 68 of file JesdTxReg.vhd.

◆ invertSync_o

invertSync_o out sl
Port

Definition at line 69 of file JesdTxReg.vhd.

◆ enableTestSig_o

enableTestSig_o out sl
Port

Definition at line 70 of file JesdTxReg.vhd.

◆ posAmplitude_o

posAmplitude_o out slv ( F_G * 8 - 1 downto 0 )
Port

Definition at line 72 of file JesdTxReg.vhd.

◆ negAmplitude_o

negAmplitude_o out slv ( F_G * 8 - 1 downto 0 )
Port

Definition at line 73 of file JesdTxReg.vhd.

◆ txDiffCtrl

txDiffCtrl out Slv8Array ( L_G - 1 downto 0 )
Port

Definition at line 76 of file JesdTxReg.vhd.

◆ txPostCursor

txPostCursor out Slv8Array ( L_G - 1 downto 0 )
Port

Definition at line 77 of file JesdTxReg.vhd.

◆ txPreCursor

txPreCursor out Slv8Array ( L_G - 1 downto 0 )
Port

Definition at line 78 of file JesdTxReg.vhd.

◆ txPolarity

txPolarity out slv ( L_G - 1 downto 0 )
Port

Definition at line 79 of file JesdTxReg.vhd.

◆ loopback

loopback out slv ( L_G - 1 downto 0 )
Port

Definition at line 80 of file JesdTxReg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file JesdTxReg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file JesdTxReg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file JesdTxReg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file JesdTxReg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file JesdTxReg.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file JesdTxReg.vhd.

◆ Jesd204bPkg

Jesd204bPkg
Package

Definition at line 25 of file JesdTxReg.vhd.

The documentation for this class was generated from the following file: