Inheritance diagram for JesdTestSigGen:
Entities | |
| rtl | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| Jesd204bPkg | Package <Jesd204bPkg> |
Generics | |
| TPD_G | time := 1 ns |
| F_G | positive := 2 |
Ports | |
| clk | in sl |
| rst | in sl |
| enable_i | in sl |
| thresoldLow_i | in slv ( ( F_G * 8 ) - 1 downto 0 ) |
| thresoldHigh_i | in slv ( ( F_G * 8 ) - 1 downto 0 ) |
| sampleData_i | in slv ( ( GT_WORD_SIZE_C * 8 ) - 1 downto 0 ) |
| testSig_o | out sl |
Detailed Description
- See also
- entity
Definition at line 30 of file JesdTestSigGen.vhd.
Member Data Documentation
◆ TPD_G
|
Generic |
Definition at line 32 of file JesdTestSigGen.vhd.
◆ F_G
|
Generic |
Definition at line 35 of file JesdTestSigGen.vhd.
◆ clk
Definition at line 37 of file JesdTestSigGen.vhd.
◆ rst
Definition at line 38 of file JesdTestSigGen.vhd.
◆ enable_i
Definition at line 41 of file JesdTestSigGen.vhd.
◆ thresoldLow_i
|
Port |
Definition at line 44 of file JesdTestSigGen.vhd.
◆ thresoldHigh_i
|
Port |
Definition at line 45 of file JesdTestSigGen.vhd.
◆ sampleData_i
|
Port |
Definition at line 48 of file JesdTestSigGen.vhd.
◆ testSig_o
Definition at line 52 of file JesdTestSigGen.vhd.
◆ ieee
|
Library |
Definition at line 20 of file JesdTestSigGen.vhd.
◆ std_logic_1164
|
Package |
Definition at line 21 of file JesdTestSigGen.vhd.
◆ std_logic_unsigned
|
Package |
Definition at line 22 of file JesdTestSigGen.vhd.
◆ std_logic_arith
|
Package |
Definition at line 23 of file JesdTestSigGen.vhd.
◆ StdRtlPkg
|
Package |
Definition at line 25 of file JesdTestSigGen.vhd.
◆ Jesd204bPkg
|
Package |
Definition at line 26 of file JesdTestSigGen.vhd.
The documentation for this class was generated from the following file:
- protocols/jesd204b/rtl/JesdTestSigGen.vhd
