SURF  1.0
Generics | Ports | Libraries | Use Clauses
JesdSysrefDly Entity Reference
protocols » jesd204b
+ Inheritance diagram for JesdSysrefDly:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
Jesd204bPkg  Package <Jesd204bPkg>

Generics

TPD_G  time := 1 ns
DLY_WIDTH_G  positive := 5

Ports

clk   in sl
rst   in sl
dly_i   in slv ( DLY_WIDTH_G - 1 downto 0 )
sysref_i   in sl
sysref_o   out sl

Detailed Description

See also
entity

Definition at line 33 of file JesdSysrefDly.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 35 of file JesdSysrefDly.vhd.

◆ DLY_WIDTH_G

DLY_WIDTH_G positive := 5
Generic

Definition at line 37 of file JesdSysrefDly.vhd.

◆ clk

clk in sl
Port

Definition at line 39 of file JesdSysrefDly.vhd.

◆ rst

rst in sl
Port

Definition at line 40 of file JesdSysrefDly.vhd.

◆ dly_i

dly_i in slv ( DLY_WIDTH_G - 1 downto 0 )
Port

Definition at line 42 of file JesdSysrefDly.vhd.

◆ sysref_i

sysref_i in sl
Port

Definition at line 45 of file JesdSysrefDly.vhd.

◆ sysref_o

sysref_o out sl
Port

Definition at line 49 of file JesdSysrefDly.vhd.

◆ ieee

ieee
Library

Definition at line 23 of file JesdSysrefDly.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 24 of file JesdSysrefDly.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 25 of file JesdSysrefDly.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 26 of file JesdSysrefDly.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 28 of file JesdSysrefDly.vhd.

◆ Jesd204bPkg

Jesd204bPkg
Package

Definition at line 29 of file JesdSysrefDly.vhd.

The documentation for this class was generated from the following file: