SURF  1.0
Generics | Ports | Libraries | Use Clauses
JesdRxReg Entity Reference
protocols » jesd204b
+ Inheritance diagram for JesdRxReg:
+ Collaboration diagram for JesdRxReg:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
Jesd204bPkg  Package <Jesd204bPkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
AXI_ADDR_WIDTH_G  positive := 10
L_G  positive range 1 to 32 := 2

Ports

axiClk_i   in sl
axiRst_i   in sl
axilReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out AxiLiteWriteSlaveType
devClk_i   in sl
devRst_i   in sl
statusRxArr_i   in rxStatuRegisterArray ( L_G - 1 downto 0 )
rawData_i   in slv32Array ( L_G - 1 downto 0 )
sysrefDlyRx_o   out slv ( SYSRF_DLY_WIDTH_C - 1 downto 0 )
enableRx_o   out slv ( L_G - 1 downto 0 )
replEnable_o   out sl
scrEnable_o   out sl
invertData_o   out slv ( L_G - 1 downto 0 )
dlyTxArr_o   out Slv4Array ( L_G - 1 downto 0 )
alignTxArr_o   out alignTxArray ( L_G - 1 downto 0 )
thresoldLowArr_o   out Slv16Array ( L_G - 1 downto 0 )
thresoldHighArr_o   out Slv16Array ( L_G - 1 downto 0 )
subClass_o   out sl
gtReset_o   out sl
clearErr_o   out sl
invertSync_o   out sl
linkErrMask_o   out slv ( 5 downto 0 )
rxPolarity   out slv ( L_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 29 of file JesdRxReg.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file JesdRxReg.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 33 of file JesdRxReg.vhd.

◆ AXI_ADDR_WIDTH_G

AXI_ADDR_WIDTH_G positive := 10
Generic

Definition at line 34 of file JesdRxReg.vhd.

◆ L_G

L_G positive range 1 to 32 := 2
Generic

Definition at line 37 of file JesdRxReg.vhd.

◆ axiClk_i

axiClk_i in sl
Port

Definition at line 40 of file JesdRxReg.vhd.

◆ axiRst_i

axiRst_i in sl
Port

Definition at line 41 of file JesdRxReg.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 44 of file JesdRxReg.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 45 of file JesdRxReg.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 46 of file JesdRxReg.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 47 of file JesdRxReg.vhd.

◆ devClk_i

devClk_i in sl
Port

Definition at line 50 of file JesdRxReg.vhd.

◆ devRst_i

devRst_i in sl
Port

Definition at line 51 of file JesdRxReg.vhd.

◆ statusRxArr_i

statusRxArr_i in rxStatuRegisterArray ( L_G - 1 downto 0 )
Port

Definition at line 55 of file JesdRxReg.vhd.

◆ rawData_i

rawData_i in slv32Array ( L_G - 1 downto 0 )
Port

Definition at line 56 of file JesdRxReg.vhd.

◆ sysrefDlyRx_o

sysrefDlyRx_o out slv ( SYSRF_DLY_WIDTH_C - 1 downto 0 )
Port

Definition at line 59 of file JesdRxReg.vhd.

◆ enableRx_o

enableRx_o out slv ( L_G - 1 downto 0 )
Port

Definition at line 60 of file JesdRxReg.vhd.

◆ replEnable_o

replEnable_o out sl
Port

Definition at line 61 of file JesdRxReg.vhd.

◆ scrEnable_o

scrEnable_o out sl
Port

Definition at line 62 of file JesdRxReg.vhd.

◆ invertData_o

invertData_o out slv ( L_G - 1 downto 0 )
Port

Definition at line 63 of file JesdRxReg.vhd.

◆ dlyTxArr_o

dlyTxArr_o out Slv4Array ( L_G - 1 downto 0 )
Port

Definition at line 64 of file JesdRxReg.vhd.

◆ alignTxArr_o

alignTxArr_o out alignTxArray ( L_G - 1 downto 0 )
Port

Definition at line 65 of file JesdRxReg.vhd.

◆ thresoldLowArr_o

thresoldLowArr_o out Slv16Array ( L_G - 1 downto 0 )
Port

Definition at line 66 of file JesdRxReg.vhd.

◆ thresoldHighArr_o

thresoldHighArr_o out Slv16Array ( L_G - 1 downto 0 )
Port

Definition at line 67 of file JesdRxReg.vhd.

◆ subClass_o

subClass_o out sl
Port

Definition at line 68 of file JesdRxReg.vhd.

◆ gtReset_o

gtReset_o out sl
Port

Definition at line 69 of file JesdRxReg.vhd.

◆ clearErr_o

clearErr_o out sl
Port

Definition at line 70 of file JesdRxReg.vhd.

◆ invertSync_o

invertSync_o out sl
Port

Definition at line 71 of file JesdRxReg.vhd.

◆ linkErrMask_o

linkErrMask_o out slv ( 5 downto 0 )
Port

Definition at line 72 of file JesdRxReg.vhd.

◆ rxPolarity

rxPolarity out slv ( L_G - 1 downto 0 )
Port

Definition at line 73 of file JesdRxReg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file JesdRxReg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file JesdRxReg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file JesdRxReg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file JesdRxReg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file JesdRxReg.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file JesdRxReg.vhd.

◆ Jesd204bPkg

Jesd204bPkg
Package

Definition at line 25 of file JesdRxReg.vhd.

The documentation for this class was generated from the following file: