SURF  1.0
JesdRxLane Entity Reference
+ Inheritance diagram for JesdRxLane:
+ Collaboration diagram for JesdRxLane:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
Jesd204bPkg  Package <Jesd204bPkg>

Generics

TPD_G  time := 1 ns
F_G  positive := 2
K_G  positive := 32

Ports

devClk_i   in sl
devRst_i   in sl
subClass_i   in sl
sysRef_i   in sl
clearErr_i   in sl
enable_i   in sl
replEnable_i   in sl
scrEnable_i   in sl
status_o   out slv ( ( RX_STAT_WIDTH_C ) - 1 downto 0 )
r_jesdGtRx   in jesdGtRxLaneType
lmfc_i   in sl
linkErrMask_i   in slv ( 5 downto 0 ) := ( others = > ' 1 ' )
nSyncAny_i   in sl
nSyncAnyD1_i   in sl
inv_i   in sl := ' 0 '
nSync_o   out sl
dataValid_o   out sl
sampleData_o   out slv ( ( GT_WORD_SIZE_C * 8 ) - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 61 of file JesdRxLane.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 63 of file JesdRxLane.vhd.

◆ F_G

F_G positive := 2
Generic

Definition at line 66 of file JesdRxLane.vhd.

◆ K_G

K_G positive := 32
Generic

Definition at line 70 of file JesdRxLane.vhd.

◆ devClk_i

devClk_i in sl
Port

Definition at line 75 of file JesdRxLane.vhd.

◆ devRst_i

devRst_i in sl
Port

Definition at line 76 of file JesdRxLane.vhd.

◆ subClass_i

subClass_i in sl
Port

Definition at line 79 of file JesdRxLane.vhd.

◆ sysRef_i

sysRef_i in sl
Port

Definition at line 82 of file JesdRxLane.vhd.

◆ clearErr_i

clearErr_i in sl
Port

Definition at line 85 of file JesdRxLane.vhd.

◆ enable_i

enable_i in sl
Port

Definition at line 88 of file JesdRxLane.vhd.

◆ replEnable_i

replEnable_i in sl
Port

Definition at line 89 of file JesdRxLane.vhd.

◆ scrEnable_i

scrEnable_i in sl
Port

Definition at line 90 of file JesdRxLane.vhd.

◆ status_o

status_o out slv ( ( RX_STAT_WIDTH_C ) - 1 downto 0 )
Port

Definition at line 91 of file JesdRxLane.vhd.

◆ r_jesdGtRx

Definition at line 94 of file JesdRxLane.vhd.

◆ lmfc_i

lmfc_i in sl
Port

Definition at line 97 of file JesdRxLane.vhd.

◆ linkErrMask_i

linkErrMask_i in slv ( 5 downto 0 ) := ( others = > ' 1 ' )
Port

Definition at line 100 of file JesdRxLane.vhd.

◆ nSyncAny_i

nSyncAny_i in sl
Port

Definition at line 103 of file JesdRxLane.vhd.

◆ nSyncAnyD1_i

nSyncAnyD1_i in sl
Port

Definition at line 104 of file JesdRxLane.vhd.

◆ inv_i

inv_i in sl := ' 0 '
Port

Definition at line 107 of file JesdRxLane.vhd.

◆ nSync_o

nSync_o out sl
Port

Definition at line 110 of file JesdRxLane.vhd.

◆ dataValid_o

dataValid_o out sl
Port

Definition at line 113 of file JesdRxLane.vhd.

◆ sampleData_o

sampleData_o out slv ( ( GT_WORD_SIZE_C * 8 ) - 1 downto 0 )
Port

Definition at line 115 of file JesdRxLane.vhd.

◆ ieee

ieee
Library

Definition at line 51 of file JesdRxLane.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 52 of file JesdRxLane.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 53 of file JesdRxLane.vhd.

◆ std_logic_unsigned

Definition at line 54 of file JesdRxLane.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 56 of file JesdRxLane.vhd.

◆ Jesd204bPkg

Jesd204bPkg
Package

Definition at line 57 of file JesdRxLane.vhd.


The documentation for this class was generated from the following file: