SURF  1.0
Generics | Ports | Libraries | Use Clauses
JesdAlignChGen Entity Reference
protocols » jesd204b
+ Inheritance diagram for JesdAlignChGen:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
jesd204bpkg 

Generics

TPD_G  time := 1 ns
F_G  positive := 2

Ports

clk   in sl
rst   in sl
enable_i   in sl
scrEnable_i   in sl
lmfc_i   in sl
dataValid_i   in sl
inv_i   in sl := ' 0 '
sampleData_i   in slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
sampleData_o   out slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
sampleK_o   out slv ( GT_WORD_SIZE_C- 1 downto 0 )

Detailed Description

See also
entity

Definition at line 41 of file JesdAlignChGen.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 43 of file JesdAlignChGen.vhd.

◆ F_G

F_G positive := 2
Generic

Definition at line 44 of file JesdAlignChGen.vhd.

◆ clk

clk in sl
Port

Definition at line 46 of file JesdAlignChGen.vhd.

◆ rst

rst in sl
Port

Definition at line 47 of file JesdAlignChGen.vhd.

◆ enable_i

enable_i in sl
Port

Definition at line 50 of file JesdAlignChGen.vhd.

◆ scrEnable_i

scrEnable_i in sl
Port

Definition at line 53 of file JesdAlignChGen.vhd.

◆ lmfc_i

lmfc_i in sl
Port

Definition at line 56 of file JesdAlignChGen.vhd.

◆ dataValid_i

dataValid_i in sl
Port

Definition at line 59 of file JesdAlignChGen.vhd.

◆ inv_i

inv_i in sl := ' 0 '
Port

Definition at line 62 of file JesdAlignChGen.vhd.

◆ sampleData_i

sampleData_i in slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
Port

Definition at line 65 of file JesdAlignChGen.vhd.

◆ sampleData_o

sampleData_o out slv ( GT_WORD_SIZE_C* 8 - 1 downto 0 )
Port

Definition at line 68 of file JesdAlignChGen.vhd.

◆ sampleK_o

sampleK_o out slv ( GT_WORD_SIZE_C- 1 downto 0 )
Port

Definition at line 70 of file JesdAlignChGen.vhd.

◆ ieee

ieee
Library

Definition at line 31 of file JesdAlignChGen.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 32 of file JesdAlignChGen.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 33 of file JesdAlignChGen.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 34 of file JesdAlignChGen.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 36 of file JesdAlignChGen.vhd.

◆ jesd204bpkg

jesd204bpkg
Package

Definition at line 37 of file JesdAlignChGen.vhd.

The documentation for this class was generated from the following file: