SURF  1.0
Generics | Ports | Libraries | Use Clauses
Jesd204bTxGtx7 Entity Reference
+ Inheritance diagram for Jesd204bTxGtx7:
+ Collaboration diagram for Jesd204bTxGtx7:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

vcomponents 
std_logic_1164 
std_logic_arith 
std_logic_unsigned 
numeric_std 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>
Jesd204bPkg  Package <Jesd204bPkg>

Generics

TPD_G  time := 1 ns
SYSREF_GEN_G  boolean := true
SIM_G  boolean := true
SIM_GTRESET_SPEEDUP_G  string := " FALSE "
SIM_VERSION_G  string := " 4.0 "
STABLE_CLOCK_PERIOD_G  real := 4 . 0E - 9
CPLL_REFCLK_SEL_G  bit_vector := " 001 "
CPLL_FBDIV_G  integer := 4
CPLL_FBDIV_45_G  integer := 4
CPLL_REFCLK_DIV_G  integer := 1
RXOUT_DIV_G  integer := 4
RX_CLK25_DIV_G  integer := 4
PMA_RSV_G  bit_vector := x " 001E7080 "
RX_OS_CFG_G  bit_vector := " 0000010000000 "
RXCDR_CFG_G  bit_vector := x " 03000023ff10400020 "
RXDFEXYDEN_G  sl := ' 1 '
RX_DFE_KL_CFG2_G  bit_vector := X " 301148AC "
TX_PLL_G  string := " QPLL "
RX_PLL_G  string := " QPLL "
TXOUT_DIV_G  integer := 2
TX_CLK25_DIV_G  integer := 7
TX_BUF_EN_G  boolean := true
TX_OUTCLK_SRC_G  string := " OUTCLKPMA "
TX_DLY_BYPASS_G  sl := ' 1 '
TX_PHASE_ALIGN_G  string := " NONE "
TX_BUF_ADDR_MODE_G  string := " FULL "
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
F_G  positive := 2
K_G  positive := 32
L_G  positive := 2

Ports

stableClk   in sl
qPllRefClkIn   in sl
qPllClkIn   in sl
qPllLockIn   in sl
qPllRefClkLostIn   in sl
qPllResetOut   out slv ( L_G - 1 downto 0 )
gtTxP   out slv ( L_G - 1 downto 0 )
gtTxN   out slv ( L_G - 1 downto 0 )
gtRxP   in slv ( L_G - 1 downto 0 )
gtRxN   in slv ( L_G - 1 downto 0 )
devClk_i   in sl
devClk2_i   in sl
devRst_i   in sl
axiClk   in sl
axiRst   in sl
axilReadMasterTx   in AxiLiteReadMasterType
axilReadSlaveTx   out AxiLiteReadSlaveType
axilWriteMasterTx   in AxiLiteWriteMasterType
axilWriteSlaveTx   out AxiLiteWriteSlaveType
txAxisMasterArr_i   in AxiStreamMasterArray ( L_G - 1 downto 0 )
txAxisSlaveArr_o   out AxiStreamSlaveArray ( L_G - 1 downto 0 )
extSampleDataArray_i   in sampleDataArray ( L_G - 1 downto 0 )
sysRef_i   in sl
sysRef_o   out sl
nSync_i   in sl
pulse_o   out slv ( L_G - 1 downto 0 )
leds_o   out slv ( 1 downto 0 )

Detailed Description

Definition at line 35 of file Jesd204bTxGtx7.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 37 of file Jesd204bTxGtx7.vhd.

◆ SYSREF_GEN_G

SYSREF_GEN_G boolean := true
Generic

Definition at line 41 of file Jesd204bTxGtx7.vhd.

◆ SIM_G

SIM_G boolean := true
Generic

Definition at line 44 of file Jesd204bTxGtx7.vhd.

◆ SIM_GTRESET_SPEEDUP_G

SIM_GTRESET_SPEEDUP_G string := " FALSE "
Generic

Definition at line 50 of file Jesd204bTxGtx7.vhd.

◆ SIM_VERSION_G

SIM_VERSION_G string := " 4.0 "
Generic

Definition at line 51 of file Jesd204bTxGtx7.vhd.

◆ STABLE_CLOCK_PERIOD_G

STABLE_CLOCK_PERIOD_G real := 4 . 0E - 9
Generic

Definition at line 52 of file Jesd204bTxGtx7.vhd.

◆ CPLL_REFCLK_SEL_G

CPLL_REFCLK_SEL_G bit_vector := " 001 "
Generic

Definition at line 55 of file Jesd204bTxGtx7.vhd.

◆ CPLL_FBDIV_G

CPLL_FBDIV_G integer := 4
Generic

Definition at line 56 of file Jesd204bTxGtx7.vhd.

◆ CPLL_FBDIV_45_G

CPLL_FBDIV_45_G integer := 4
Generic

Definition at line 57 of file Jesd204bTxGtx7.vhd.

◆ CPLL_REFCLK_DIV_G

CPLL_REFCLK_DIV_G integer := 1
Generic

Definition at line 58 of file Jesd204bTxGtx7.vhd.

◆ RXOUT_DIV_G

RXOUT_DIV_G integer := 4
Generic

Definition at line 60 of file Jesd204bTxGtx7.vhd.

◆ RX_CLK25_DIV_G

RX_CLK25_DIV_G integer := 4
Generic

Definition at line 61 of file Jesd204bTxGtx7.vhd.

◆ PMA_RSV_G

PMA_RSV_G bit_vector := x " 001E7080 "
Generic

Definition at line 64 of file Jesd204bTxGtx7.vhd.

◆ RX_OS_CFG_G

RX_OS_CFG_G bit_vector := " 0000010000000 "
Generic

Definition at line 65 of file Jesd204bTxGtx7.vhd.

◆ RXCDR_CFG_G

RXCDR_CFG_G bit_vector := x " 03000023ff10400020 "
Generic

Definition at line 66 of file Jesd204bTxGtx7.vhd.

◆ RXDFEXYDEN_G

RXDFEXYDEN_G sl := ' 1 '
Generic

Definition at line 67 of file Jesd204bTxGtx7.vhd.

◆ RX_DFE_KL_CFG2_G

RX_DFE_KL_CFG2_G bit_vector := X " 301148AC "
Generic

Definition at line 68 of file Jesd204bTxGtx7.vhd.

◆ TX_PLL_G

TX_PLL_G string := " QPLL "
Generic

Definition at line 71 of file Jesd204bTxGtx7.vhd.

◆ RX_PLL_G

RX_PLL_G string := " QPLL "
Generic

Definition at line 72 of file Jesd204bTxGtx7.vhd.

◆ TXOUT_DIV_G

TXOUT_DIV_G integer := 2
Generic

Definition at line 75 of file Jesd204bTxGtx7.vhd.

◆ TX_CLK25_DIV_G

TX_CLK25_DIV_G integer := 7
Generic

Definition at line 76 of file Jesd204bTxGtx7.vhd.

◆ TX_BUF_EN_G

TX_BUF_EN_G boolean := true
Generic

Definition at line 77 of file Jesd204bTxGtx7.vhd.

◆ TX_OUTCLK_SRC_G

TX_OUTCLK_SRC_G string := " OUTCLKPMA "
Generic

Definition at line 78 of file Jesd204bTxGtx7.vhd.

◆ TX_DLY_BYPASS_G

TX_DLY_BYPASS_G sl := ' 1 '
Generic

Definition at line 79 of file Jesd204bTxGtx7.vhd.

◆ TX_PHASE_ALIGN_G

TX_PHASE_ALIGN_G string := " NONE "
Generic

Definition at line 80 of file Jesd204bTxGtx7.vhd.

◆ TX_BUF_ADDR_MODE_G

TX_BUF_ADDR_MODE_G string := " FULL "
Generic

Definition at line 81 of file Jesd204bTxGtx7.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 85 of file Jesd204bTxGtx7.vhd.

◆ F_G

F_G positive := 2
Generic

Definition at line 89 of file Jesd204bTxGtx7.vhd.

◆ K_G

K_G positive := 32
Generic

Definition at line 90 of file Jesd204bTxGtx7.vhd.

◆ L_G

L_G positive := 2
Generic

Definition at line 92 of file Jesd204bTxGtx7.vhd.

◆ stableClk

stableClk in sl
Port

Definition at line 98 of file Jesd204bTxGtx7.vhd.

◆ qPllRefClkIn

qPllRefClkIn in sl
Port

Definition at line 101 of file Jesd204bTxGtx7.vhd.

◆ qPllClkIn

qPllClkIn in sl
Port

Definition at line 102 of file Jesd204bTxGtx7.vhd.

◆ qPllLockIn

qPllLockIn in sl
Port

Definition at line 103 of file Jesd204bTxGtx7.vhd.

◆ qPllRefClkLostIn

qPllRefClkLostIn in sl
Port

Definition at line 104 of file Jesd204bTxGtx7.vhd.

◆ qPllResetOut

qPllResetOut out slv ( L_G - 1 downto 0 )
Port

Definition at line 105 of file Jesd204bTxGtx7.vhd.

◆ gtTxP

gtTxP out slv ( L_G - 1 downto 0 )
Port

Definition at line 108 of file Jesd204bTxGtx7.vhd.

◆ gtTxN

gtTxN out slv ( L_G - 1 downto 0 )
Port

Definition at line 109 of file Jesd204bTxGtx7.vhd.

◆ gtRxP

gtRxP in slv ( L_G - 1 downto 0 )
Port

Definition at line 110 of file Jesd204bTxGtx7.vhd.

◆ gtRxN

gtRxN in slv ( L_G - 1 downto 0 )
Port

Definition at line 111 of file Jesd204bTxGtx7.vhd.

◆ devClk_i

devClk_i in sl
Port

Definition at line 115 of file Jesd204bTxGtx7.vhd.

◆ devClk2_i

devClk2_i in sl
Port

Definition at line 116 of file Jesd204bTxGtx7.vhd.

◆ devRst_i

devRst_i in sl
Port

Definition at line 117 of file Jesd204bTxGtx7.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 121 of file Jesd204bTxGtx7.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 122 of file Jesd204bTxGtx7.vhd.

◆ axilReadMasterTx

axilReadMasterTx in AxiLiteReadMasterType
Port

Definition at line 125 of file Jesd204bTxGtx7.vhd.

◆ axilReadSlaveTx

axilReadSlaveTx out AxiLiteReadSlaveType
Port

Definition at line 126 of file Jesd204bTxGtx7.vhd.

◆ axilWriteMasterTx

axilWriteMasterTx in AxiLiteWriteMasterType
Port

Definition at line 127 of file Jesd204bTxGtx7.vhd.

◆ axilWriteSlaveTx

axilWriteSlaveTx out AxiLiteWriteSlaveType
Port

Definition at line 128 of file Jesd204bTxGtx7.vhd.

◆ txAxisMasterArr_i

txAxisMasterArr_i in AxiStreamMasterArray ( L_G - 1 downto 0 )
Port

Definition at line 131 of file Jesd204bTxGtx7.vhd.

◆ txAxisSlaveArr_o

txAxisSlaveArr_o out AxiStreamSlaveArray ( L_G - 1 downto 0 )
Port

Definition at line 132 of file Jesd204bTxGtx7.vhd.

◆ extSampleDataArray_i

extSampleDataArray_i in sampleDataArray ( L_G - 1 downto 0 )
Port

Definition at line 135 of file Jesd204bTxGtx7.vhd.

◆ sysRef_i

sysRef_i in sl
Port

Definition at line 141 of file Jesd204bTxGtx7.vhd.

◆ sysRef_o

sysRef_o out sl
Port

Definition at line 144 of file Jesd204bTxGtx7.vhd.

◆ nSync_i

nSync_i in sl
Port

Definition at line 147 of file Jesd204bTxGtx7.vhd.

◆ pulse_o

pulse_o out slv ( L_G - 1 downto 0 )
Port

Definition at line 150 of file Jesd204bTxGtx7.vhd.

◆ leds_o

leds_o out slv ( 1 downto 0 )
Port

Definition at line 154 of file Jesd204bTxGtx7.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file Jesd204bTxGtx7.vhd.

◆ unisim

unisim
Library

Definition at line 21 of file Jesd204bTxGtx7.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 22 of file Jesd204bTxGtx7.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 24 of file Jesd204bTxGtx7.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 25 of file Jesd204bTxGtx7.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 26 of file Jesd204bTxGtx7.vhd.

◆ numeric_std

numeric_std
Package

Definition at line 27 of file Jesd204bTxGtx7.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 29 of file Jesd204bTxGtx7.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 30 of file Jesd204bTxGtx7.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 31 of file Jesd204bTxGtx7.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 32 of file Jesd204bTxGtx7.vhd.

◆ Jesd204bPkg

Jesd204bPkg
Package

Definition at line 33 of file Jesd204bTxGtx7.vhd.

The documentation for this class was generated from the following file: