SURF  1.0
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Jesd204bTx Entity Reference
protocols » jesd204b
+ Inheritance diagram for Jesd204bTx:
+ Collaboration diagram for Jesd204bTx:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>
Jesd204bPkg  Package <Jesd204bPkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
INPUT_REG_G  boolean := false
OUTPUT_REG_G  boolean := false
F_G  positive := 2
K_G  positive := 32
L_G  positive range 1 to 32 := 2

Ports

axiClk   in sl
axiRst   in sl
axilReadMaster   in AxiLiteReadMasterType
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType
axilWriteSlave   out AxiLiteWriteSlaveType
txAxisMasterArr_i   in AxiStreamMasterArray ( L_G - 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
txAxisSlaveArr_o   out AxiStreamSlaveArray ( L_G - 1 downto 0 )
devClk_i   in sl
devRst_i   in sl
sysRef_i   in sl
nSync_i   in sl
extSampleDataArray_i   in sampleDataArray ( L_G - 1 downto 0 )
gtTxReset_o   out slv ( L_G - 1 downto 0 )
gtTxReady_i   in slv ( L_G - 1 downto 0 )
r_jesdGtTxArr   out jesdGtTxLaneTypeArray ( L_G - 1 downto 0 )
txDiffCtrl   out Slv8Array ( L_G - 1 downto 0 )
txPostCursor   out Slv8Array ( L_G - 1 downto 0 )
txPreCursor   out Slv8Array ( L_G - 1 downto 0 )
txPolarity   out slv ( L_G - 1 downto 0 )
loopback   out slv ( L_G - 1 downto 0 )
txEnable   out slv ( L_G - 1 downto 0 )
txEnableL   out slv ( L_G - 1 downto 0 )
pulse_o   out slv ( L_G - 1 downto 0 )
leds_o   out slv ( 1 downto 0 )

Detailed Description

See also
entity

Definition at line 44 of file Jesd204bTx.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 46 of file Jesd204bTx.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 47 of file Jesd204bTx.vhd.

◆ INPUT_REG_G

INPUT_REG_G boolean := false
Generic

Definition at line 49 of file Jesd204bTx.vhd.

◆ OUTPUT_REG_G

OUTPUT_REG_G boolean := false
Generic

Definition at line 50 of file Jesd204bTx.vhd.

◆ F_G

F_G positive := 2
Generic

Definition at line 52 of file Jesd204bTx.vhd.

◆ K_G

K_G positive := 32
Generic

Definition at line 54 of file Jesd204bTx.vhd.

◆ L_G

L_G positive range 1 to 32 := 2
Generic

Definition at line 56 of file Jesd204bTx.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 60 of file Jesd204bTx.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 61 of file Jesd204bTx.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType
Port

Definition at line 64 of file Jesd204bTx.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 65 of file Jesd204bTx.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 66 of file Jesd204bTx.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 67 of file Jesd204bTx.vhd.

◆ txAxisMasterArr_i

txAxisMasterArr_i in AxiStreamMasterArray ( L_G - 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
Port

Definition at line 70 of file Jesd204bTx.vhd.

◆ txAxisSlaveArr_o

txAxisSlaveArr_o out AxiStreamSlaveArray ( L_G - 1 downto 0 )
Port

Definition at line 71 of file Jesd204bTx.vhd.

◆ devClk_i

devClk_i in sl
Port

Definition at line 75 of file Jesd204bTx.vhd.

◆ devRst_i

devRst_i in sl
Port

Definition at line 76 of file Jesd204bTx.vhd.

◆ sysRef_i

sysRef_i in sl
Port

Definition at line 79 of file Jesd204bTx.vhd.

◆ nSync_i

nSync_i in sl
Port

Definition at line 82 of file Jesd204bTx.vhd.

◆ extSampleDataArray_i

extSampleDataArray_i in sampleDataArray ( L_G - 1 downto 0 )
Port

Definition at line 85 of file Jesd204bTx.vhd.

◆ gtTxReset_o

gtTxReset_o out slv ( L_G - 1 downto 0 )
Port

Definition at line 88 of file Jesd204bTx.vhd.

◆ gtTxReady_i

gtTxReady_i in slv ( L_G - 1 downto 0 )
Port

Definition at line 89 of file Jesd204bTx.vhd.

◆ r_jesdGtTxArr

r_jesdGtTxArr out jesdGtTxLaneTypeArray ( L_G - 1 downto 0 )
Port

Definition at line 92 of file Jesd204bTx.vhd.

◆ txDiffCtrl

txDiffCtrl out Slv8Array ( L_G - 1 downto 0 )
Port

Definition at line 95 of file Jesd204bTx.vhd.

◆ txPostCursor

txPostCursor out Slv8Array ( L_G - 1 downto 0 )
Port

Definition at line 96 of file Jesd204bTx.vhd.

◆ txPreCursor

txPreCursor out Slv8Array ( L_G - 1 downto 0 )
Port

Definition at line 97 of file Jesd204bTx.vhd.

◆ txPolarity

txPolarity out slv ( L_G - 1 downto 0 )
Port

Definition at line 98 of file Jesd204bTx.vhd.

◆ loopback

loopback out slv ( L_G - 1 downto 0 )
Port

Definition at line 99 of file Jesd204bTx.vhd.

◆ txEnable

txEnable out slv ( L_G - 1 downto 0 )
Port

Definition at line 100 of file Jesd204bTx.vhd.

◆ txEnableL

txEnableL out slv ( L_G - 1 downto 0 )
Port

Definition at line 101 of file Jesd204bTx.vhd.

◆ pulse_o

pulse_o out slv ( L_G - 1 downto 0 )
Port

Definition at line 104 of file Jesd204bTx.vhd.

◆ leds_o

leds_o out slv ( 1 downto 0 )
Port

Definition at line 105 of file Jesd204bTx.vhd.

◆ ieee

ieee
Library

Definition at line 30 of file Jesd204bTx.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 31 of file Jesd204bTx.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 32 of file Jesd204bTx.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 33 of file Jesd204bTx.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 35 of file Jesd204bTx.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 36 of file Jesd204bTx.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 37 of file Jesd204bTx.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 38 of file Jesd204bTx.vhd.

◆ Jesd204bPkg

Jesd204bPkg
Package

Definition at line 40 of file Jesd204bTx.vhd.

The documentation for this class was generated from the following file: