Inheritance diagram for Iprog7Series:
Collaboration diagram for Iprog7Series:
Entities | |
| rtl | architecture |
Libraries | |
| ieee | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| vcomponents | |
Generics | |
| TPD_G | time := 1 ns |
| USE_SLOWCLK_G | boolean := false |
| BUFR_CLK_DIV_G | string := " 8 " |
Ports | |
| clk | in sl |
| rst | in sl |
| slowClk | in sl := ' 0 ' |
| start | in sl |
| bootAddress | in slv ( 31 downto 0 ) := X " 00000000 " |
Detailed Description
- See also
- entity
Definition at line 33 of file Iprog7Series.vhd.
Member Data Documentation
◆ TPD_G
|
Generic |
Definition at line 35 of file Iprog7Series.vhd.
◆ USE_SLOWCLK_G
|
Generic |
Definition at line 36 of file Iprog7Series.vhd.
◆ BUFR_CLK_DIV_G
|
Generic |
Definition at line 37 of file Iprog7Series.vhd.
◆ clk
Definition at line 39 of file Iprog7Series.vhd.
◆ rst
Definition at line 40 of file Iprog7Series.vhd.
◆ slowClk
Definition at line 41 of file Iprog7Series.vhd.
◆ start
Definition at line 42 of file Iprog7Series.vhd.
◆ bootAddress
|
Port |
Definition at line 43 of file Iprog7Series.vhd.
◆ ieee
|
Library |
Definition at line 21 of file Iprog7Series.vhd.
◆ std_logic_1164
|
Package |
Definition at line 22 of file Iprog7Series.vhd.
◆ std_logic_arith
|
Package |
Definition at line 23 of file Iprog7Series.vhd.
◆ std_logic_unsigned
|
Package |
Definition at line 24 of file Iprog7Series.vhd.
◆ StdRtlPkg
|
Package |
Definition at line 26 of file Iprog7Series.vhd.
◆ unisim
|
Library |
Definition at line 28 of file Iprog7Series.vhd.
◆ vcomponents
|
Package |
Definition at line 29 of file Iprog7Series.vhd.
The documentation for this class was generated from the following file:
- xilinx/7Series/general/rtl/Iprog7Series.vhd
