SURF  1.0
Generics | Ports | Libraries | Use Clauses
IpV4EngineRx Entity Reference
ethernet » IpV4Engine
+ Inheritance diagram for IpV4EngineRx:
+ Collaboration diagram for IpV4EngineRx:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>
EthMacPkg  Package <EthMacPkg>

Generics

TPD_G  time := 1 ns
SIM_ERROR_HALT_G  boolean := false
PROTOCOL_SIZE_G  positive := 1
PROTOCOL_G  Slv8Array := ( 0 = > UDP_C )
VLAN_G  boolean := false

Ports

ibIpv4Master   in AxiStreamMasterType
ibIpv4Slave   out AxiStreamSlaveType
localhostMaster   in AxiStreamMasterType
localhostSlave   out AxiStreamSlaveType
ibProtocolMasters   out AxiStreamMasterArray ( PROTOCOL_SIZE_G - 1 downto 0 )
ibProtocolSlaves   in AxiStreamSlaveArray ( PROTOCOL_SIZE_G - 1 downto 0 )
clk   in sl
rst   in sl

Detailed Description

See also
entity

Definition at line 31 of file IpV4EngineRx.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file IpV4EngineRx.vhd.

◆ SIM_ERROR_HALT_G

SIM_ERROR_HALT_G boolean := false
Generic

Definition at line 34 of file IpV4EngineRx.vhd.

◆ PROTOCOL_SIZE_G

PROTOCOL_SIZE_G positive := 1
Generic

Definition at line 35 of file IpV4EngineRx.vhd.

◆ PROTOCOL_G

PROTOCOL_G Slv8Array := ( 0 = > UDP_C )
Generic

Definition at line 36 of file IpV4EngineRx.vhd.

◆ VLAN_G

VLAN_G boolean := false
Generic

Definition at line 37 of file IpV4EngineRx.vhd.

◆ ibIpv4Master

ibIpv4Master in AxiStreamMasterType
Port

Definition at line 40 of file IpV4EngineRx.vhd.

◆ ibIpv4Slave

ibIpv4Slave out AxiStreamSlaveType
Port

Definition at line 41 of file IpV4EngineRx.vhd.

◆ localhostMaster

localhostMaster in AxiStreamMasterType
Port

Definition at line 42 of file IpV4EngineRx.vhd.

◆ localhostSlave

localhostSlave out AxiStreamSlaveType
Port

Definition at line 43 of file IpV4EngineRx.vhd.

◆ ibProtocolMasters

ibProtocolMasters out AxiStreamMasterArray ( PROTOCOL_SIZE_G - 1 downto 0 )
Port

Definition at line 45 of file IpV4EngineRx.vhd.

◆ ibProtocolSlaves

ibProtocolSlaves in AxiStreamSlaveArray ( PROTOCOL_SIZE_G - 1 downto 0 )
Port

Definition at line 46 of file IpV4EngineRx.vhd.

◆ clk

clk in sl
Port

Definition at line 48 of file IpV4EngineRx.vhd.

◆ rst

rst in sl
Port

Definition at line 49 of file IpV4EngineRx.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file IpV4EngineRx.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file IpV4EngineRx.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file IpV4EngineRx.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file IpV4EngineRx.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file IpV4EngineRx.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 25 of file IpV4EngineRx.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 26 of file IpV4EngineRx.vhd.

◆ EthMacPkg

EthMacPkg
Package

Definition at line 27 of file IpV4EngineRx.vhd.

The documentation for this class was generated from the following file: