SURF  1.0
I2cRegMasterAxiBridge Entity Reference
+ Inheritance diagram for I2cRegMasterAxiBridge:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
I2cPkg  Package <I2cPkg>

Generics

TPD_G  time := 1 ns
DEVICE_MAP_G  I2cAxiLiteDevArray := I2C_AXIL_DEV_ARRAY_DEFAULT_C
EN_USER_REG_G  boolean := false
NUM_WRITE_REG_G  integer range 1 to 128 := 1
NUM_READ_REG_G  integer range 1 to 128 := 1
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

axiClk   in sl
axiRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
readRegister   in Slv32Array ( 0 to NUM_READ_REG_G ) := ( others = > x " 00000000 " )
writeRegisterInit   in Slv32Array ( 0 to NUM_WRITE_REG_G ) := ( others = > x " 00000000 " )
writeRegister   out Slv32Array ( 0 to NUM_WRITE_REG_G )
i2cRegMasterIn   out I2cRegMasterInType
i2cRegMasterOut   in I2cRegMasterOutType

Detailed Description

See also
entity

Definition at line 29 of file I2cRegMasterAxiBridge.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file I2cRegMasterAxiBridge.vhd.

◆ DEVICE_MAP_G

◆ EN_USER_REG_G

EN_USER_REG_G boolean := false
Generic

Definition at line 34 of file I2cRegMasterAxiBridge.vhd.

◆ NUM_WRITE_REG_G

NUM_WRITE_REG_G integer range 1 to 128 := 1
Generic

Definition at line 35 of file I2cRegMasterAxiBridge.vhd.

◆ NUM_READ_REG_G

NUM_READ_REG_G integer range 1 to 128 := 1
Generic

Definition at line 36 of file I2cRegMasterAxiBridge.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 37 of file I2cRegMasterAxiBridge.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 40 of file I2cRegMasterAxiBridge.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 41 of file I2cRegMasterAxiBridge.vhd.

◆ axiReadMaster

Definition at line 43 of file I2cRegMasterAxiBridge.vhd.

◆ axiReadSlave

Definition at line 44 of file I2cRegMasterAxiBridge.vhd.

◆ axiWriteMaster

◆ axiWriteSlave

Definition at line 46 of file I2cRegMasterAxiBridge.vhd.

◆ readRegister

readRegister in Slv32Array ( 0 to NUM_READ_REG_G ) := ( others = > x " 00000000 " )
Port

Definition at line 49 of file I2cRegMasterAxiBridge.vhd.

◆ writeRegisterInit

writeRegisterInit in Slv32Array ( 0 to NUM_WRITE_REG_G ) := ( others = > x " 00000000 " )
Port

Definition at line 50 of file I2cRegMasterAxiBridge.vhd.

◆ writeRegister

Definition at line 51 of file I2cRegMasterAxiBridge.vhd.

◆ i2cRegMasterIn

Definition at line 53 of file I2cRegMasterAxiBridge.vhd.

◆ i2cRegMasterOut

Definition at line 54 of file I2cRegMasterAxiBridge.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file I2cRegMasterAxiBridge.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file I2cRegMasterAxiBridge.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file I2cRegMasterAxiBridge.vhd.

◆ std_logic_unsigned

Definition at line 21 of file I2cRegMasterAxiBridge.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file I2cRegMasterAxiBridge.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file I2cRegMasterAxiBridge.vhd.

◆ I2cPkg

I2cPkg
Package

Definition at line 25 of file I2cRegMasterAxiBridge.vhd.


The documentation for this class was generated from the following file: