GigEthReg Entity Reference

Inheritance diagram for GigEthReg:

Collaboration diagram for GigEthReg:

Entities
rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
GigEthPkg	Package <GigEthPkg>

Generics
TPD_G	time := 1 ns
EN_AXI_REG_G	boolean := false
AXI_ERROR_RESP_G	slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports
localMac	in slv ( 47 downto 0 ) := MAC_ADDR_INIT_C
clk	in sl
rst	in sl
axiReadMaster	in AxiLiteReadMasterType
axiReadSlave	out AxiLiteReadSlaveType
axiWriteMaster	in AxiLiteWriteMasterType
axiWriteSlave	out AxiLiteWriteSlaveType
config	out GigEthConfigType
status	in GigEthStatusType

Detailed Description

See also

entity

Definition at line 29 of file GigEthReg.vhd.

Member Data Documentation

TPD_G

TPD_G time := 1 ns

Generic

Definition at line 31 of file GigEthReg.vhd.

EN_AXI_REG_G

EN_AXI_REG_G boolean := false

Generic

Definition at line 32 of file GigEthReg.vhd.

AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Generic

Definition at line 33 of file GigEthReg.vhd.

localMac

localMac in slv ( 47 downto 0 ) := MAC_ADDR_INIT_C

Port

Definition at line 36 of file GigEthReg.vhd.

clk

clk in sl

Port

Definition at line 38 of file GigEthReg.vhd.

rst

rst in sl

Port

Definition at line 39 of file GigEthReg.vhd.

axiReadMaster

axiReadMaster in AxiLiteReadMasterType

Port

Definition at line 41 of file GigEthReg.vhd.

axiReadSlave

axiReadSlave out AxiLiteReadSlaveType

Port

Definition at line 42 of file GigEthReg.vhd.

axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType

Port

Definition at line 43 of file GigEthReg.vhd.

axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType

Port

Definition at line 44 of file GigEthReg.vhd.

config

config out GigEthConfigType

Port

Definition at line 46 of file GigEthReg.vhd.

status

status in GigEthStatusType

Port

Definition at line 47 of file GigEthReg.vhd.

ieee

ieee

Library

Definition at line 18 of file GigEthReg.vhd.

std_logic_1164

std_logic_1164

Package

Definition at line 19 of file GigEthReg.vhd.

std_logic_unsigned

std_logic_unsigned

Package

Definition at line 20 of file GigEthReg.vhd.

std_logic_arith

std_logic_arith

Package

Definition at line 21 of file GigEthReg.vhd.

StdRtlPkg

StdRtlPkg

Package

Definition at line 23 of file GigEthReg.vhd.

AxiLitePkg

AxiLitePkg

Package

Definition at line 24 of file GigEthReg.vhd.

GigEthPkg

GigEthPkg

Package

Definition at line 25 of file GigEthReg.vhd.

---

The documentation for this class was generated from the following file:

• ethernet/GigEthCore/core/rtl/GigEthReg.vhd