SURF  1.0
Generics | Ports | Libraries | Use Clauses
FifoMux Entity Reference
base » fifo
+ Inheritance diagram for FifoMux:
+ Collaboration diagram for FifoMux:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
CASCADE_SIZE_G  integer range 1 to ( 2 ** 24 ) := 1
LAST_STAGE_ASYNC_G  boolean := true
RST_POLARITY_G  sl := ' 1 '
RST_ASYNC_G  boolean := false
GEN_SYNC_FIFO_G  boolean := false
BRAM_EN_G  boolean := true
FWFT_EN_G  boolean := true
USE_DSP48_G  string := " no "
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
USE_BUILT_IN_G  boolean := false
XIL_DEVICE_G  string := " 7SERIES "
SYNC_STAGES_G  integer range 3 to ( 2 ** 24 ) := 3
PIPE_STAGES_G  natural range 0 to 16 := 0
WR_DATA_WIDTH_G  integer range 1 to ( 2 ** 24 ) := 64
RD_DATA_WIDTH_G  integer range 1 to ( 2 ** 24 ) := 16
LITTLE_ENDIAN_G  boolean := false
ADDR_WIDTH_G  integer range 4 to 48 := 10
INIT_G  slv := " 0 "
FULL_THRES_G  integer range 1 to ( 2 ** 24 ) := 1
EMPTY_THRES_G  integer range 1 to ( 2 ** 24 ) := 1

Ports

rst   in sl := ' 0 '
wr_clk   in sl
wr_en   in sl := ' 0 '
din   in slv ( WR_DATA_WIDTH_G - 1 downto 0 )
wr_data_count   out slv ( ADDR_WIDTH_G - 1 downto 0 )
wr_ack   out sl
overflow   out sl
prog_full   out sl
almost_full   out sl
full   out sl
not_full   out sl
rd_clk   in sl
rd_en   in sl := ' 0 '
dout   out slv ( RD_DATA_WIDTH_G - 1 downto 0 )
rd_data_count   out slv ( ADDR_WIDTH_G - 1 downto 0 )
valid   out sl
underflow   out sl
prog_empty   out sl
almost_empty   out sl
empty   out sl

Detailed Description

See also
entity

Definition at line 26 of file FifoMux.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 28 of file FifoMux.vhd.

◆ CASCADE_SIZE_G

CASCADE_SIZE_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 29 of file FifoMux.vhd.

◆ LAST_STAGE_ASYNC_G

LAST_STAGE_ASYNC_G boolean := true
Generic

Definition at line 30 of file FifoMux.vhd.

◆ RST_POLARITY_G

RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 31 of file FifoMux.vhd.

◆ RST_ASYNC_G

RST_ASYNC_G boolean := false
Generic

Definition at line 32 of file FifoMux.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 33 of file FifoMux.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 34 of file FifoMux.vhd.

◆ FWFT_EN_G

FWFT_EN_G boolean := true
Generic

Definition at line 35 of file FifoMux.vhd.

◆ USE_DSP48_G

USE_DSP48_G string := " no "
Generic

Definition at line 36 of file FifoMux.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 37 of file FifoMux.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 38 of file FifoMux.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 39 of file FifoMux.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 40 of file FifoMux.vhd.

◆ SYNC_STAGES_G

SYNC_STAGES_G integer range 3 to ( 2 ** 24 ) := 3
Generic

Definition at line 41 of file FifoMux.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G natural range 0 to 16 := 0
Generic

Definition at line 42 of file FifoMux.vhd.

◆ WR_DATA_WIDTH_G

WR_DATA_WIDTH_G integer range 1 to ( 2 ** 24 ) := 64
Generic

Definition at line 43 of file FifoMux.vhd.

◆ RD_DATA_WIDTH_G

RD_DATA_WIDTH_G integer range 1 to ( 2 ** 24 ) := 16
Generic

Definition at line 44 of file FifoMux.vhd.

◆ LITTLE_ENDIAN_G

LITTLE_ENDIAN_G boolean := false
Generic

Definition at line 45 of file FifoMux.vhd.

◆ ADDR_WIDTH_G

ADDR_WIDTH_G integer range 4 to 48 := 10
Generic

Definition at line 46 of file FifoMux.vhd.

◆ INIT_G

INIT_G slv := " 0 "
Generic

Definition at line 47 of file FifoMux.vhd.

◆ FULL_THRES_G

FULL_THRES_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 48 of file FifoMux.vhd.

◆ EMPTY_THRES_G

EMPTY_THRES_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 49 of file FifoMux.vhd.

◆ rst

rst in sl := ' 0 '
Port

Definition at line 52 of file FifoMux.vhd.

◆ wr_clk

wr_clk in sl
Port

Definition at line 54 of file FifoMux.vhd.

◆ wr_en

wr_en in sl := ' 0 '
Port

Definition at line 55 of file FifoMux.vhd.

◆ din

din in slv ( WR_DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 56 of file FifoMux.vhd.

◆ wr_data_count

wr_data_count out slv ( ADDR_WIDTH_G - 1 downto 0 )
Port

Definition at line 57 of file FifoMux.vhd.

◆ wr_ack

wr_ack out sl
Port

Definition at line 58 of file FifoMux.vhd.

◆ overflow

overflow out sl
Port

Definition at line 59 of file FifoMux.vhd.

◆ prog_full

prog_full out sl
Port

Definition at line 60 of file FifoMux.vhd.

◆ almost_full

almost_full out sl
Port

Definition at line 61 of file FifoMux.vhd.

◆ full

full out sl
Port

Definition at line 62 of file FifoMux.vhd.

◆ not_full

not_full out sl
Port

Definition at line 63 of file FifoMux.vhd.

◆ rd_clk

rd_clk in sl
Port

Definition at line 65 of file FifoMux.vhd.

◆ rd_en

rd_en in sl := ' 0 '
Port

Definition at line 66 of file FifoMux.vhd.

◆ dout

dout out slv ( RD_DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 67 of file FifoMux.vhd.

◆ rd_data_count

rd_data_count out slv ( ADDR_WIDTH_G - 1 downto 0 )
Port

Definition at line 68 of file FifoMux.vhd.

◆ valid

valid out sl
Port

Definition at line 69 of file FifoMux.vhd.

◆ underflow

underflow out sl
Port

Definition at line 70 of file FifoMux.vhd.

◆ prog_empty

prog_empty out sl
Port

Definition at line 71 of file FifoMux.vhd.

◆ almost_empty

almost_empty out sl
Port

Definition at line 72 of file FifoMux.vhd.

◆ empty

empty out sl
Port

Definition at line 73 of file FifoMux.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file FifoMux.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file FifoMux.vhd.

◆ numeric_std

numeric_std
Package

Definition at line 20 of file FifoMux.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 22 of file FifoMux.vhd.

The documentation for this class was generated from the following file: