SURF  1.0
Generics | Ports | Libraries | Use Clauses
DeviceDnaUltraScale Entity Reference
xilinx » UltraScale » general
+ Inheritance diagram for DeviceDnaUltraScale:
+ Collaboration diagram for DeviceDnaUltraScale:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
vcomponents 

Generics

TPD_G  time := 1 ns
USE_SLOWCLK_G  boolean := false
BUFR_CLK_DIV_G  natural := 8
RST_POLARITY_G  sl := ' 1 '
SIM_DNA_VALUE_G  slv := X " 000000000000000000000000 "

Ports

clk   in sl
rst   in sl
slowClk   in sl := ' 0 '
dnaValue   out slv ( 95 downto 0 )
dnaValid   out sl

Detailed Description

See also
entity

Definition at line 30 of file DeviceDnaUltraScale.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file DeviceDnaUltraScale.vhd.

◆ USE_SLOWCLK_G

USE_SLOWCLK_G boolean := false
Generic

Definition at line 33 of file DeviceDnaUltraScale.vhd.

◆ BUFR_CLK_DIV_G

BUFR_CLK_DIV_G natural := 8
Generic

Definition at line 34 of file DeviceDnaUltraScale.vhd.

◆ RST_POLARITY_G

RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 35 of file DeviceDnaUltraScale.vhd.

◆ SIM_DNA_VALUE_G

SIM_DNA_VALUE_G slv := X " 000000000000000000000000 "
Generic

Definition at line 36 of file DeviceDnaUltraScale.vhd.

◆ clk

clk in sl
Port

Definition at line 38 of file DeviceDnaUltraScale.vhd.

◆ rst

rst in sl
Port

Definition at line 39 of file DeviceDnaUltraScale.vhd.

◆ slowClk

slowClk in sl := ' 0 '
Port

Definition at line 40 of file DeviceDnaUltraScale.vhd.

◆ dnaValue

dnaValue out slv ( 95 downto 0 )
Port

Definition at line 41 of file DeviceDnaUltraScale.vhd.

◆ dnaValid

dnaValid out sl
Port

Definition at line 42 of file DeviceDnaUltraScale.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file DeviceDnaUltraScale.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file DeviceDnaUltraScale.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file DeviceDnaUltraScale.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file DeviceDnaUltraScale.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file DeviceDnaUltraScale.vhd.

◆ unisim

unisim
Library

Definition at line 25 of file DeviceDnaUltraScale.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 26 of file DeviceDnaUltraScale.vhd.

The documentation for this class was generated from the following file: