SURF  1.0
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ClockManagerUltraScale Entity Reference
xilinx » UltraScale » general
+ Inheritance diagram for ClockManagerUltraScale:
+ Collaboration diagram for ClockManagerUltraScale:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
vcomponents 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
TYPE_G  string := " MMCM "
INPUT_BUFG_G  boolean := true
FB_BUFG_G  boolean := true
RST_IN_POLARITY_G  sl := ' 1 '
NUM_CLOCKS_G  integer range 1 to 7
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
BANDWIDTH_G  string := " OPTIMIZED "
CLKIN_PERIOD_G  real := 10 . 0
DIVCLK_DIVIDE_G  integer range 1 to 106 := 1
CLKFBOUT_MULT_F_G  real range 1 . 0 to 64 . 0 := 1 . 0
CLKFBOUT_MULT_G  integer range 2 to 64 := 5
CLKOUT0_DIVIDE_F_G  real range 1 . 0 to 128 . 0 := 1 . 0
CLKOUT0_DIVIDE_G  integer range 1 to 128 := 1
CLKOUT1_DIVIDE_G  integer range 1 to 128 := 1
CLKOUT2_DIVIDE_G  integer range 1 to 128 := 1
CLKOUT3_DIVIDE_G  integer range 1 to 128 := 1
CLKOUT4_DIVIDE_G  integer range 1 to 128 := 1
CLKOUT5_DIVIDE_G  integer range 1 to 128 := 1
CLKOUT6_DIVIDE_G  integer range 1 to 128 := 1
CLKOUT0_PHASE_G  real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT1_PHASE_G  real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT2_PHASE_G  real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT3_PHASE_G  real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT4_PHASE_G  real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT5_PHASE_G  real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT6_PHASE_G  real range - 360 . 0 to 360 . 0 := 0 . 0
CLKOUT0_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT1_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT2_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT3_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT4_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT5_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT6_DUTY_CYCLE_G  real range 0 . 01 to 0 . 99 := 0 . 5
CLKOUT0_RST_HOLD_G  integer range 3 to positive ' high := 3
CLKOUT1_RST_HOLD_G  integer range 3 to positive ' high := 3
CLKOUT2_RST_HOLD_G  integer range 3 to positive ' high := 3
CLKOUT3_RST_HOLD_G  integer range 3 to positive ' high := 3
CLKOUT4_RST_HOLD_G  integer range 3 to positive ' high := 3
CLKOUT5_RST_HOLD_G  integer range 3 to positive ' high := 3
CLKOUT6_RST_HOLD_G  integer range 3 to positive ' high := 3
CLKOUT0_RST_POLARITY_G  sl := ' 1 '
CLKOUT1_RST_POLARITY_G  sl := ' 1 '
CLKOUT2_RST_POLARITY_G  sl := ' 1 '
CLKOUT3_RST_POLARITY_G  sl := ' 1 '
CLKOUT4_RST_POLARITY_G  sl := ' 1 '
CLKOUT5_RST_POLARITY_G  sl := ' 1 '
CLKOUT6_RST_POLARITY_G  sl := ' 1 '

Ports

clkIn   in sl
rstIn   in sl := ' 0 '
clkOut   out slv ( NUM_CLOCKS_G - 1 downto 0 )
rstOut   out slv ( NUM_CLOCKS_G - 1 downto 0 )
locked   out sl
axilClk   in sl := ' 0 '
axilRst   in sl := ' 0 '
axilReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 31 of file ClockManagerUltraScale.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file ClockManagerUltraScale.vhd.

◆ TYPE_G

TYPE_G string := " MMCM "
Generic

Definition at line 34 of file ClockManagerUltraScale.vhd.

◆ INPUT_BUFG_G

INPUT_BUFG_G boolean := true
Generic

Definition at line 35 of file ClockManagerUltraScale.vhd.

◆ FB_BUFG_G

FB_BUFG_G boolean := true
Generic

Definition at line 36 of file ClockManagerUltraScale.vhd.

◆ RST_IN_POLARITY_G

RST_IN_POLARITY_G sl := ' 1 '
Generic

Definition at line 37 of file ClockManagerUltraScale.vhd.

◆ NUM_CLOCKS_G

NUM_CLOCKS_G integer range 1 to 7
Generic

Definition at line 38 of file ClockManagerUltraScale.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 39 of file ClockManagerUltraScale.vhd.

◆ BANDWIDTH_G

BANDWIDTH_G string := " OPTIMIZED "
Generic

Definition at line 41 of file ClockManagerUltraScale.vhd.

◆ CLKIN_PERIOD_G

CLKIN_PERIOD_G real := 10 . 0
Generic

Definition at line 42 of file ClockManagerUltraScale.vhd.

◆ DIVCLK_DIVIDE_G

DIVCLK_DIVIDE_G integer range 1 to 106 := 1
Generic

Definition at line 43 of file ClockManagerUltraScale.vhd.

◆ CLKFBOUT_MULT_F_G

CLKFBOUT_MULT_F_G real range 1 . 0 to 64 . 0 := 1 . 0
Generic

Definition at line 44 of file ClockManagerUltraScale.vhd.

◆ CLKFBOUT_MULT_G

CLKFBOUT_MULT_G integer range 2 to 64 := 5
Generic

Definition at line 45 of file ClockManagerUltraScale.vhd.

◆ CLKOUT0_DIVIDE_F_G

CLKOUT0_DIVIDE_F_G real range 1 . 0 to 128 . 0 := 1 . 0
Generic

Definition at line 46 of file ClockManagerUltraScale.vhd.

◆ CLKOUT0_DIVIDE_G

CLKOUT0_DIVIDE_G integer range 1 to 128 := 1
Generic

Definition at line 47 of file ClockManagerUltraScale.vhd.

◆ CLKOUT1_DIVIDE_G

CLKOUT1_DIVIDE_G integer range 1 to 128 := 1
Generic

Definition at line 48 of file ClockManagerUltraScale.vhd.

◆ CLKOUT2_DIVIDE_G

CLKOUT2_DIVIDE_G integer range 1 to 128 := 1
Generic

Definition at line 49 of file ClockManagerUltraScale.vhd.

◆ CLKOUT3_DIVIDE_G

CLKOUT3_DIVIDE_G integer range 1 to 128 := 1
Generic

Definition at line 50 of file ClockManagerUltraScale.vhd.

◆ CLKOUT4_DIVIDE_G

CLKOUT4_DIVIDE_G integer range 1 to 128 := 1
Generic

Definition at line 51 of file ClockManagerUltraScale.vhd.

◆ CLKOUT5_DIVIDE_G

CLKOUT5_DIVIDE_G integer range 1 to 128 := 1
Generic

Definition at line 52 of file ClockManagerUltraScale.vhd.

◆ CLKOUT6_DIVIDE_G

CLKOUT6_DIVIDE_G integer range 1 to 128 := 1
Generic

Definition at line 53 of file ClockManagerUltraScale.vhd.

◆ CLKOUT0_PHASE_G

CLKOUT0_PHASE_G real range - 360 . 0 to 360 . 0 := 0 . 0
Generic

Definition at line 54 of file ClockManagerUltraScale.vhd.

◆ CLKOUT1_PHASE_G

CLKOUT1_PHASE_G real range - 360 . 0 to 360 . 0 := 0 . 0
Generic

Definition at line 55 of file ClockManagerUltraScale.vhd.

◆ CLKOUT2_PHASE_G

CLKOUT2_PHASE_G real range - 360 . 0 to 360 . 0 := 0 . 0
Generic

Definition at line 56 of file ClockManagerUltraScale.vhd.

◆ CLKOUT3_PHASE_G

CLKOUT3_PHASE_G real range - 360 . 0 to 360 . 0 := 0 . 0
Generic

Definition at line 57 of file ClockManagerUltraScale.vhd.

◆ CLKOUT4_PHASE_G

CLKOUT4_PHASE_G real range - 360 . 0 to 360 . 0 := 0 . 0
Generic

Definition at line 58 of file ClockManagerUltraScale.vhd.

◆ CLKOUT5_PHASE_G

CLKOUT5_PHASE_G real range - 360 . 0 to 360 . 0 := 0 . 0
Generic

Definition at line 59 of file ClockManagerUltraScale.vhd.

◆ CLKOUT6_PHASE_G

CLKOUT6_PHASE_G real range - 360 . 0 to 360 . 0 := 0 . 0
Generic

Definition at line 60 of file ClockManagerUltraScale.vhd.

◆ CLKOUT0_DUTY_CYCLE_G

CLKOUT0_DUTY_CYCLE_G real range 0 . 01 to 0 . 99 := 0 . 5
Generic

Definition at line 61 of file ClockManagerUltraScale.vhd.

◆ CLKOUT1_DUTY_CYCLE_G

CLKOUT1_DUTY_CYCLE_G real range 0 . 01 to 0 . 99 := 0 . 5
Generic

Definition at line 62 of file ClockManagerUltraScale.vhd.

◆ CLKOUT2_DUTY_CYCLE_G

CLKOUT2_DUTY_CYCLE_G real range 0 . 01 to 0 . 99 := 0 . 5
Generic

Definition at line 63 of file ClockManagerUltraScale.vhd.

◆ CLKOUT3_DUTY_CYCLE_G

CLKOUT3_DUTY_CYCLE_G real range 0 . 01 to 0 . 99 := 0 . 5
Generic

Definition at line 64 of file ClockManagerUltraScale.vhd.

◆ CLKOUT4_DUTY_CYCLE_G

CLKOUT4_DUTY_CYCLE_G real range 0 . 01 to 0 . 99 := 0 . 5
Generic

Definition at line 65 of file ClockManagerUltraScale.vhd.

◆ CLKOUT5_DUTY_CYCLE_G

CLKOUT5_DUTY_CYCLE_G real range 0 . 01 to 0 . 99 := 0 . 5
Generic

Definition at line 66 of file ClockManagerUltraScale.vhd.

◆ CLKOUT6_DUTY_CYCLE_G

CLKOUT6_DUTY_CYCLE_G real range 0 . 01 to 0 . 99 := 0 . 5
Generic

Definition at line 67 of file ClockManagerUltraScale.vhd.

◆ CLKOUT0_RST_HOLD_G

CLKOUT0_RST_HOLD_G integer range 3 to positive ' high := 3
Generic

Definition at line 68 of file ClockManagerUltraScale.vhd.

◆ CLKOUT1_RST_HOLD_G

CLKOUT1_RST_HOLD_G integer range 3 to positive ' high := 3
Generic

Definition at line 69 of file ClockManagerUltraScale.vhd.

◆ CLKOUT2_RST_HOLD_G

CLKOUT2_RST_HOLD_G integer range 3 to positive ' high := 3
Generic

Definition at line 70 of file ClockManagerUltraScale.vhd.

◆ CLKOUT3_RST_HOLD_G

CLKOUT3_RST_HOLD_G integer range 3 to positive ' high := 3
Generic

Definition at line 71 of file ClockManagerUltraScale.vhd.

◆ CLKOUT4_RST_HOLD_G

CLKOUT4_RST_HOLD_G integer range 3 to positive ' high := 3
Generic

Definition at line 72 of file ClockManagerUltraScale.vhd.

◆ CLKOUT5_RST_HOLD_G

CLKOUT5_RST_HOLD_G integer range 3 to positive ' high := 3
Generic

Definition at line 73 of file ClockManagerUltraScale.vhd.

◆ CLKOUT6_RST_HOLD_G

CLKOUT6_RST_HOLD_G integer range 3 to positive ' high := 3
Generic

Definition at line 74 of file ClockManagerUltraScale.vhd.

◆ CLKOUT0_RST_POLARITY_G

CLKOUT0_RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 75 of file ClockManagerUltraScale.vhd.

◆ CLKOUT1_RST_POLARITY_G

CLKOUT1_RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 76 of file ClockManagerUltraScale.vhd.

◆ CLKOUT2_RST_POLARITY_G

CLKOUT2_RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 77 of file ClockManagerUltraScale.vhd.

◆ CLKOUT3_RST_POLARITY_G

CLKOUT3_RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 78 of file ClockManagerUltraScale.vhd.

◆ CLKOUT4_RST_POLARITY_G

CLKOUT4_RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 79 of file ClockManagerUltraScale.vhd.

◆ CLKOUT5_RST_POLARITY_G

CLKOUT5_RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 80 of file ClockManagerUltraScale.vhd.

◆ CLKOUT6_RST_POLARITY_G

CLKOUT6_RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 81 of file ClockManagerUltraScale.vhd.

◆ clkIn

clkIn in sl
Port

Definition at line 83 of file ClockManagerUltraScale.vhd.

◆ rstIn

rstIn in sl := ' 0 '
Port

Definition at line 84 of file ClockManagerUltraScale.vhd.

◆ clkOut

clkOut out slv ( NUM_CLOCKS_G - 1 downto 0 )
Port

Definition at line 85 of file ClockManagerUltraScale.vhd.

◆ rstOut

rstOut out slv ( NUM_CLOCKS_G - 1 downto 0 )
Port

Definition at line 86 of file ClockManagerUltraScale.vhd.

◆ locked

locked out sl
Port

Definition at line 87 of file ClockManagerUltraScale.vhd.

◆ axilClk

axilClk in sl := ' 0 '
Port

Definition at line 89 of file ClockManagerUltraScale.vhd.

◆ axilRst

axilRst in sl := ' 0 '
Port

Definition at line 90 of file ClockManagerUltraScale.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 91 of file ClockManagerUltraScale.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 92 of file ClockManagerUltraScale.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 93 of file ClockManagerUltraScale.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 94 of file ClockManagerUltraScale.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file ClockManagerUltraScale.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file ClockManagerUltraScale.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file ClockManagerUltraScale.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file ClockManagerUltraScale.vhd.

◆ unisim

unisim
Library

Definition at line 23 of file ClockManagerUltraScale.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 24 of file ClockManagerUltraScale.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 26 of file ClockManagerUltraScale.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 27 of file ClockManagerUltraScale.vhd.

The documentation for this class was generated from the following file: