SURF  1.0
Generics | Ports | Libraries | Use Clauses
CRC32Rtl Entity Reference
base » general
+ Inheritance diagram for CRC32Rtl:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 

Generics

CRC_INIT  bit_vector := x " FFFFFFFF "

Ports

CRCOUT   out std_logic_vector ( 31 downto 0 )
CRCCLK   in std_logic
CRCCLKEN   in std_logic := ' 1 '
CRCDATAVALID   in std_logic
CRCDATAWIDTH   in std_logic_vector ( 2 downto 0 )
CRCIN   in std_logic_vector ( 31 downto 0 )
CRCRESET   in std_logic

Detailed Description

See also
entity

Definition at line 33 of file CRC32Rtl.vhd.

Member Data Documentation

◆ CRC_INIT

CRC_INIT bit_vector := x " FFFFFFFF "
Generic

Definition at line 35 of file CRC32Rtl.vhd.

◆ CRCOUT

CRCOUT out std_logic_vector ( 31 downto 0 )
Port

Definition at line 37 of file CRC32Rtl.vhd.

◆ CRCCLK

CRCCLK in std_logic
Port

Definition at line 38 of file CRC32Rtl.vhd.

◆ CRCCLKEN

CRCCLKEN in std_logic := ' 1 '
Port

Definition at line 39 of file CRC32Rtl.vhd.

◆ CRCDATAVALID

CRCDATAVALID in std_logic
Port

Definition at line 40 of file CRC32Rtl.vhd.

◆ CRCDATAWIDTH

CRCDATAWIDTH in std_logic_vector ( 2 downto 0 )
Port

Definition at line 41 of file CRC32Rtl.vhd.

◆ CRCIN

CRCIN in std_logic_vector ( 31 downto 0 )
Port

Definition at line 42 of file CRC32Rtl.vhd.

◆ CRCRESET

CRCRESET in std_logic
Port

Definition at line 43 of file CRC32Rtl.vhd.

◆ ieee

ieee
Library

Definition at line 26 of file CRC32Rtl.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 27 of file CRC32Rtl.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 28 of file CRC32Rtl.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 29 of file CRC32Rtl.vhd.

The documentation for this class was generated from the following file: