SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiWritePathFifo Entity Reference
axi
+ Inheritance diagram for AxiWritePathFifo:
+ Collaboration diagram for AxiWritePathFifo:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiPkg  Package <AxiPkg>

Generics

TPD_G  time := 1 ns
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
GEN_SYNC_FIFO_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
ADDR_LSB_G  natural range 0 to 31 := 0
ID_FIXED_EN_G  boolean := false
SIZE_FIXED_EN_G  boolean := false
BURST_FIXED_EN_G  boolean := false
LEN_FIXED_EN_G  boolean := false
LOCK_FIXED_EN_G  boolean := false
PROT_FIXED_EN_G  boolean := false
CACHE_FIXED_EN_G  boolean := false
ADDR_BRAM_EN_G  boolean := true
ADDR_CASCADE_SIZE_G  integer range 1 to ( 2 ** 24 ) := 1
ADDR_FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 9
DATA_BRAM_EN_G  boolean := true
DATA_CASCADE_SIZE_G  integer range 1 to ( 2 ** 24 ) := 1
DATA_FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 9
DATA_FIFO_PAUSE_THRESH_G  integer range 1 to ( 2 ** 24 ) := 500
RESP_BRAM_EN_G  boolean := true
RESP_CASCADE_SIZE_G  integer range 1 to ( 2 ** 24 ) := 1
RESP_FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 9
AXI_CONFIG_G  AxiConfigType := AXI_CONFIG_INIT_C

Ports

sAxiClk   in sl
sAxiRst   in sl
sAxiWriteMaster   in AxiWriteMasterType
sAxiWriteSlave   out AxiWriteSlaveType
sAxiCtrl   out AxiCtrlType
mAxiClk   in sl
mAxiRst   in sl
mAxiWriteMaster   out AxiWriteMasterType
mAxiWriteSlave   in AxiWriteSlaveType

Detailed Description

See also
entity

Definition at line 29 of file AxiWritePathFifo.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file AxiWritePathFifo.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 36 of file AxiWritePathFifo.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 37 of file AxiWritePathFifo.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 38 of file AxiWritePathFifo.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 39 of file AxiWritePathFifo.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 40 of file AxiWritePathFifo.vhd.

◆ ADDR_LSB_G

ADDR_LSB_G natural range 0 to 31 := 0
Generic

Definition at line 43 of file AxiWritePathFifo.vhd.

◆ ID_FIXED_EN_G

ID_FIXED_EN_G boolean := false
Generic

Definition at line 44 of file AxiWritePathFifo.vhd.

◆ SIZE_FIXED_EN_G

SIZE_FIXED_EN_G boolean := false
Generic

Definition at line 45 of file AxiWritePathFifo.vhd.

◆ BURST_FIXED_EN_G

BURST_FIXED_EN_G boolean := false
Generic

Definition at line 46 of file AxiWritePathFifo.vhd.

◆ LEN_FIXED_EN_G

LEN_FIXED_EN_G boolean := false
Generic

Definition at line 47 of file AxiWritePathFifo.vhd.

◆ LOCK_FIXED_EN_G

LOCK_FIXED_EN_G boolean := false
Generic

Definition at line 48 of file AxiWritePathFifo.vhd.

◆ PROT_FIXED_EN_G

PROT_FIXED_EN_G boolean := false
Generic

Definition at line 49 of file AxiWritePathFifo.vhd.

◆ CACHE_FIXED_EN_G

CACHE_FIXED_EN_G boolean := false
Generic

Definition at line 50 of file AxiWritePathFifo.vhd.

◆ ADDR_BRAM_EN_G

ADDR_BRAM_EN_G boolean := true
Generic

Definition at line 53 of file AxiWritePathFifo.vhd.

◆ ADDR_CASCADE_SIZE_G

ADDR_CASCADE_SIZE_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 54 of file AxiWritePathFifo.vhd.

◆ ADDR_FIFO_ADDR_WIDTH_G

ADDR_FIFO_ADDR_WIDTH_G integer range 4 to 48 := 9
Generic

Definition at line 55 of file AxiWritePathFifo.vhd.

◆ DATA_BRAM_EN_G

DATA_BRAM_EN_G boolean := true
Generic

Definition at line 58 of file AxiWritePathFifo.vhd.

◆ DATA_CASCADE_SIZE_G

DATA_CASCADE_SIZE_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 59 of file AxiWritePathFifo.vhd.

◆ DATA_FIFO_ADDR_WIDTH_G

DATA_FIFO_ADDR_WIDTH_G integer range 4 to 48 := 9
Generic

Definition at line 60 of file AxiWritePathFifo.vhd.

◆ DATA_FIFO_PAUSE_THRESH_G

DATA_FIFO_PAUSE_THRESH_G integer range 1 to ( 2 ** 24 ) := 500
Generic

Definition at line 61 of file AxiWritePathFifo.vhd.

◆ RESP_BRAM_EN_G

RESP_BRAM_EN_G boolean := true
Generic

Definition at line 64 of file AxiWritePathFifo.vhd.

◆ RESP_CASCADE_SIZE_G

RESP_CASCADE_SIZE_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 65 of file AxiWritePathFifo.vhd.

◆ RESP_FIFO_ADDR_WIDTH_G

RESP_FIFO_ADDR_WIDTH_G integer range 4 to 48 := 9
Generic

Definition at line 66 of file AxiWritePathFifo.vhd.

◆ AXI_CONFIG_G

AXI_CONFIG_G AxiConfigType := AXI_CONFIG_INIT_C
Generic

Definition at line 70 of file AxiWritePathFifo.vhd.

◆ sAxiClk

sAxiClk in sl
Port

Definition at line 74 of file AxiWritePathFifo.vhd.

◆ sAxiRst

sAxiRst in sl
Port

Definition at line 75 of file AxiWritePathFifo.vhd.

◆ sAxiWriteMaster

sAxiWriteMaster in AxiWriteMasterType
Port

Definition at line 76 of file AxiWritePathFifo.vhd.

◆ sAxiWriteSlave

sAxiWriteSlave out AxiWriteSlaveType
Port

Definition at line 77 of file AxiWritePathFifo.vhd.

◆ sAxiCtrl

sAxiCtrl out AxiCtrlType
Port

Definition at line 78 of file AxiWritePathFifo.vhd.

◆ mAxiClk

mAxiClk in sl
Port

Definition at line 81 of file AxiWritePathFifo.vhd.

◆ mAxiRst

mAxiRst in sl
Port

Definition at line 82 of file AxiWritePathFifo.vhd.

◆ mAxiWriteMaster

mAxiWriteMaster out AxiWriteMasterType
Port

Definition at line 83 of file AxiWritePathFifo.vhd.

◆ mAxiWriteSlave

mAxiWriteSlave in AxiWriteSlaveType
Port

Definition at line 84 of file AxiWritePathFifo.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file AxiWritePathFifo.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file AxiWritePathFifo.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file AxiWritePathFifo.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file AxiWritePathFifo.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file AxiWritePathFifo.vhd.

◆ AxiPkg

AxiPkg
Package

Definition at line 25 of file AxiWritePathFifo.vhd.

The documentation for this class was generated from the following file: