SURF  1.0
AxiWriteEmulate Entity Reference
+ Inheritance diagram for AxiWriteEmulate:
+ Collaboration diagram for AxiWriteEmulate:

Entities

structure  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
TextUtilPkg  Package <TextUtilPkg>
StdRtlPkg  Package <StdRtlPkg>
AxiPkg  Package <AxiPkg>

Generics

TPD_G  time := 1 ns
LATENCY_G  natural := 31
AXI_CONFIG_G  AxiConfigType := AXI_CONFIG_INIT_C
SIM_DEBUG_G  boolean := false

Ports

axiClk   in sl
axiRst   in sl
axiWriteMaster   in AxiWriteMasterType
axiWriteSlave   out AxiWriteSlaveType

Detailed Description

See also
entity

Definition at line 29 of file AxiWriteEmulate.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file AxiWriteEmulate.vhd.

◆ LATENCY_G

LATENCY_G natural := 31
Generic

Definition at line 32 of file AxiWriteEmulate.vhd.

◆ AXI_CONFIG_G

Definition at line 33 of file AxiWriteEmulate.vhd.

◆ SIM_DEBUG_G

SIM_DEBUG_G boolean := false
Generic

Definition at line 34 of file AxiWriteEmulate.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 37 of file AxiWriteEmulate.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 38 of file AxiWriteEmulate.vhd.

◆ axiWriteMaster

Definition at line 40 of file AxiWriteEmulate.vhd.

◆ axiWriteSlave

Definition at line 41 of file AxiWriteEmulate.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiWriteEmulate.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiWriteEmulate.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file AxiWriteEmulate.vhd.

◆ std_logic_unsigned

Definition at line 21 of file AxiWriteEmulate.vhd.

◆ TextUtilPkg

TextUtilPkg
Package

Definition at line 23 of file AxiWriteEmulate.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file AxiWriteEmulate.vhd.

◆ AxiPkg

AxiPkg
Package

Definition at line 25 of file AxiWriteEmulate.vhd.


The documentation for this class was generated from the following file: