SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiVersion Entity Reference
axi
+ Inheritance diagram for AxiVersion:
+ Collaboration diagram for AxiVersion:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
BUILD_INFO_G  BuildInfoType
SIM_DNA_VALUE_G  slv := X " 000000000000000000000000 "
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
DEVICE_ID_G  slv ( 31 downto 0 ) := ( others = > ' 0 ' )
CLK_PERIOD_G  real := 8 . 0E - 9
XIL_DEVICE_G  string := " 7SERIES "
EN_DEVICE_DNA_G  boolean := false
EN_DS2411_G  boolean := false
EN_ICAP_G  boolean := false
USE_SLOWCLK_G  boolean := false
BUFR_CLK_DIV_G  positive := 8
AUTO_RELOAD_EN_G  boolean := false
AUTO_RELOAD_TIME_G  real range 0 . 0 to 30 . 0 := 10 . 0
AUTO_RELOAD_ADDR_G  slv ( 31 downto 0 ) := ( others = > ' 0 ' )

Ports

axiClk   in sl
axiRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
masterReset   out sl
fpgaEnReload   in sl := ' 1 '
fpgaReload   out sl
fpgaReloadAddr   out slv ( 31 downto 0 )
upTimeCnt   out slv ( 31 downto 0 )
slowClk   in sl := ' 0 '
dnaValueOut   out slv ( 127 downto 0 )
fdValueOut   out slv ( 63 downto 0 )
userValues   in Slv32Array ( 0 to 63 ) := ( others = > X " 00000000 " )
fdSerSdio   inout sl := ' Z '

Detailed Description

See also
entity

Definition at line 29 of file AxiVersion.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file AxiVersion.vhd.

◆ BUILD_INFO_G

BUILD_INFO_G BuildInfoType
Generic

Definition at line 32 of file AxiVersion.vhd.

◆ SIM_DNA_VALUE_G

SIM_DNA_VALUE_G slv := X " 000000000000000000000000 "
Generic

Definition at line 33 of file AxiVersion.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 34 of file AxiVersion.vhd.

◆ DEVICE_ID_G

DEVICE_ID_G slv ( 31 downto 0 ) := ( others = > ' 0 ' )
Generic

Definition at line 35 of file AxiVersion.vhd.

◆ CLK_PERIOD_G

CLK_PERIOD_G real := 8 . 0E - 9
Generic

Definition at line 36 of file AxiVersion.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 37 of file AxiVersion.vhd.

◆ EN_DEVICE_DNA_G

EN_DEVICE_DNA_G boolean := false
Generic

Definition at line 38 of file AxiVersion.vhd.

◆ EN_DS2411_G

EN_DS2411_G boolean := false
Generic

Definition at line 39 of file AxiVersion.vhd.

◆ EN_ICAP_G

EN_ICAP_G boolean := false
Generic

Definition at line 40 of file AxiVersion.vhd.

◆ USE_SLOWCLK_G

USE_SLOWCLK_G boolean := false
Generic

Definition at line 41 of file AxiVersion.vhd.

◆ BUFR_CLK_DIV_G

BUFR_CLK_DIV_G positive := 8
Generic

Definition at line 42 of file AxiVersion.vhd.

◆ AUTO_RELOAD_EN_G

AUTO_RELOAD_EN_G boolean := false
Generic

Definition at line 43 of file AxiVersion.vhd.

◆ AUTO_RELOAD_TIME_G

AUTO_RELOAD_TIME_G real range 0 . 0 to 30 . 0 := 10 . 0
Generic

Definition at line 44 of file AxiVersion.vhd.

◆ AUTO_RELOAD_ADDR_G

AUTO_RELOAD_ADDR_G slv ( 31 downto 0 ) := ( others = > ' 0 ' )
Generic

Definition at line 45 of file AxiVersion.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 48 of file AxiVersion.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 49 of file AxiVersion.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 50 of file AxiVersion.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 51 of file AxiVersion.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 52 of file AxiVersion.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 53 of file AxiVersion.vhd.

◆ masterReset

masterReset out sl
Port

Definition at line 55 of file AxiVersion.vhd.

◆ fpgaEnReload

fpgaEnReload in sl := ' 1 '
Port

Definition at line 57 of file AxiVersion.vhd.

◆ fpgaReload

fpgaReload out sl
Port

Definition at line 58 of file AxiVersion.vhd.

◆ fpgaReloadAddr

fpgaReloadAddr out slv ( 31 downto 0 )
Port

Definition at line 59 of file AxiVersion.vhd.

◆ upTimeCnt

upTimeCnt out slv ( 31 downto 0 )
Port

Definition at line 60 of file AxiVersion.vhd.

◆ slowClk

slowClk in sl := ' 0 '
Port

Definition at line 62 of file AxiVersion.vhd.

◆ dnaValueOut

dnaValueOut out slv ( 127 downto 0 )
Port

Definition at line 63 of file AxiVersion.vhd.

◆ fdValueOut

fdValueOut out slv ( 63 downto 0 )
Port

Definition at line 64 of file AxiVersion.vhd.

◆ userValues

userValues in Slv32Array ( 0 to 63 ) := ( others = > X " 00000000 " )
Port

Definition at line 66 of file AxiVersion.vhd.

◆ fdSerSdio

fdSerSdio inout sl := ' Z '
Port

Definition at line 68 of file AxiVersion.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file AxiVersion.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file AxiVersion.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiVersion.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 22 of file AxiVersion.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file AxiVersion.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 25 of file AxiVersion.vhd.

The documentation for this class was generated from the following file: