SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiSy56040Reg Entity Reference
devices » Microchip » sy56040
+ Inheritance diagram for AxiSy56040Reg:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
AXI_CLK_FREQ_G  real := 200 . 0E + 6
XBAR_DEFAULT_G  Slv2Array ( 3 downto 0 ) := ( " 11 " , " 10 " , " 01 " , " 00 " )
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

xBarSin   out slv ( 1 downto 0 )
xBarSout   out slv ( 1 downto 0 )
xBarConfig   out sl
xBarLoad   out sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl

Detailed Description

See also
entity

Definition at line 28 of file AxiSy56040Reg.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file AxiSy56040Reg.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 31 of file AxiSy56040Reg.vhd.

◆ XBAR_DEFAULT_G

XBAR_DEFAULT_G Slv2Array ( 3 downto 0 ) := ( " 11 " , " 10 " , " 01 " , " 00 " )
Generic

Definition at line 32 of file AxiSy56040Reg.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 33 of file AxiSy56040Reg.vhd.

◆ xBarSin

xBarSin out slv ( 1 downto 0 )
Port

Definition at line 36 of file AxiSy56040Reg.vhd.

◆ xBarSout

xBarSout out slv ( 1 downto 0 )
Port

Definition at line 37 of file AxiSy56040Reg.vhd.

◆ xBarConfig

xBarConfig out sl
Port

Definition at line 38 of file AxiSy56040Reg.vhd.

◆ xBarLoad

xBarLoad out sl
Port

Definition at line 39 of file AxiSy56040Reg.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 41 of file AxiSy56040Reg.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 42 of file AxiSy56040Reg.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 43 of file AxiSy56040Reg.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 44 of file AxiSy56040Reg.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 46 of file AxiSy56040Reg.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 47 of file AxiSy56040Reg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiSy56040Reg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiSy56040Reg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiSy56040Reg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiSy56040Reg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiSy56040Reg.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiSy56040Reg.vhd.

The documentation for this class was generated from the following file: