SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiStreamFifo Entity Reference
axi
+ Inheritance diagram for AxiStreamFifo:
+ Collaboration diagram for AxiStreamFifo:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>

Generics

TPD_G  time := 1 ns
INT_PIPE_STAGES_G  natural range 0 to 16 := 0
PIPE_STAGES_G  natural range 0 to 16 := 1
SLAVE_READY_EN_G  boolean := true
VALID_THOLD_G  integer range 0 to ( 2 ** 24 ) := 1
BRAM_EN_G  boolean := true
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
GEN_SYNC_FIFO_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
CASCADE_SIZE_G  integer range 1 to ( 2 ** 24 ) := 1
FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 9
FIFO_FIXED_THRESH_G  boolean := true
FIFO_PAUSE_THRESH_G  integer range 1 to ( 2 ** 24 ) := 1
LAST_FIFO_ADDR_WIDTH_G  integer range 0 to 48 := 0
CASCADE_PAUSE_SEL_G  integer range 0 to ( 2 ** 24 ) := 0
SLAVE_AXI_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
MASTER_AXI_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C

Ports

sAxisClk   in sl
sAxisRst   in sl
sAxisMaster   in AxiStreamMasterType
sAxisSlave   out AxiStreamSlaveType
sAxisCtrl   out AxiStreamCtrlType
fifoPauseThresh   in slv ( FIFO_ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 1 ' )
mAxisClk   in sl
mAxisRst   in sl
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
mTLastTUser   out slv ( 127 downto 0 )

Detailed Description

See also
entity

Definition at line 31 of file AxiStreamFifo.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 35 of file AxiStreamFifo.vhd.

◆ INT_PIPE_STAGES_G

INT_PIPE_STAGES_G natural range 0 to 16 := 0
Generic

Definition at line 36 of file AxiStreamFifo.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G natural range 0 to 16 := 1
Generic

Definition at line 37 of file AxiStreamFifo.vhd.

◆ SLAVE_READY_EN_G

SLAVE_READY_EN_G boolean := true
Generic

Definition at line 38 of file AxiStreamFifo.vhd.

◆ VALID_THOLD_G

VALID_THOLD_G integer range 0 to ( 2 ** 24 ) := 1
Generic

Definition at line 39 of file AxiStreamFifo.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 43 of file AxiStreamFifo.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 44 of file AxiStreamFifo.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 45 of file AxiStreamFifo.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 46 of file AxiStreamFifo.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 47 of file AxiStreamFifo.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 48 of file AxiStreamFifo.vhd.

◆ CASCADE_SIZE_G

CASCADE_SIZE_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 49 of file AxiStreamFifo.vhd.

◆ FIFO_ADDR_WIDTH_G

FIFO_ADDR_WIDTH_G integer range 4 to 48 := 9
Generic

Definition at line 50 of file AxiStreamFifo.vhd.

◆ FIFO_FIXED_THRESH_G

FIFO_FIXED_THRESH_G boolean := true
Generic

Definition at line 51 of file AxiStreamFifo.vhd.

◆ FIFO_PAUSE_THRESH_G

FIFO_PAUSE_THRESH_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 52 of file AxiStreamFifo.vhd.

◆ LAST_FIFO_ADDR_WIDTH_G

LAST_FIFO_ADDR_WIDTH_G integer range 0 to 48 := 0
Generic

Definition at line 58 of file AxiStreamFifo.vhd.

◆ CASCADE_PAUSE_SEL_G

CASCADE_PAUSE_SEL_G integer range 0 to ( 2 ** 24 ) := 0
Generic

Definition at line 61 of file AxiStreamFifo.vhd.

◆ SLAVE_AXI_CONFIG_G

SLAVE_AXI_CONFIG_G AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Generic

Definition at line 64 of file AxiStreamFifo.vhd.

◆ MASTER_AXI_CONFIG_G

MASTER_AXI_CONFIG_G AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Generic

Definition at line 66 of file AxiStreamFifo.vhd.

◆ sAxisClk

sAxisClk in sl
Port

Definition at line 70 of file AxiStreamFifo.vhd.

◆ sAxisRst

sAxisRst in sl
Port

Definition at line 71 of file AxiStreamFifo.vhd.

◆ sAxisMaster

sAxisMaster in AxiStreamMasterType
Port

Definition at line 72 of file AxiStreamFifo.vhd.

◆ sAxisSlave

sAxisSlave out AxiStreamSlaveType
Port

Definition at line 73 of file AxiStreamFifo.vhd.

◆ sAxisCtrl

sAxisCtrl out AxiStreamCtrlType
Port

Definition at line 74 of file AxiStreamFifo.vhd.

◆ fifoPauseThresh

fifoPauseThresh in slv ( FIFO_ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 1 ' )
Port

Definition at line 77 of file AxiStreamFifo.vhd.

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 80 of file AxiStreamFifo.vhd.

◆ mAxisRst

mAxisRst in sl
Port

Definition at line 81 of file AxiStreamFifo.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 82 of file AxiStreamFifo.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType
Port

Definition at line 83 of file AxiStreamFifo.vhd.

◆ mTLastTUser

mTLastTUser out slv ( 127 downto 0 )
Port

Definition at line 84 of file AxiStreamFifo.vhd.

◆ ieee

ieee
Library

Definition at line 21 of file AxiStreamFifo.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 22 of file AxiStreamFifo.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 23 of file AxiStreamFifo.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 24 of file AxiStreamFifo.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 26 of file AxiStreamFifo.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 27 of file AxiStreamFifo.vhd.

The documentation for this class was generated from the following file: