SURF  1.0
AxiStreamDmaV2Read Entity Reference
+ Inheritance diagram for AxiStreamDmaV2Read:
+ Collaboration diagram for AxiStreamDmaV2Read:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiPkg  Package <AxiPkg>
AxiDmaPkg  Package <AxiDmaPkg>

Generics

TPD_G  time := 1 ns
AXIS_READY_EN_G  boolean := false
AXIS_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
AXI_CONFIG_G  AxiConfigType := AXI_CONFIG_INIT_C
PIPE_STAGES_G  natural := 1
BURST_BYTES_G  integer range 1 to 4096 := 4096
PEND_THRESH_G  natural := 0

Ports

axiClk   in sl
axiRst   in sl
dmaRdDescReq   in AxiReadDmaDescReqType
dmaRdDescAck   out sl
dmaRdDescRet   out AxiReadDmaDescRetType
dmaRdDescRetAck   in sl
dmaRdIdle   out sl
axiCache   in slv ( 3 downto 0 )
axisMaster   out AxiStreamMasterType
axisSlave   in AxiStreamSlaveType
axisCtrl   in AxiStreamCtrlType
axiReadMaster   out AxiReadMasterType
axiReadSlave   in AxiReadSlaveType

Detailed Description

See also
entity

Definition at line 32 of file AxiStreamDmaV2Read.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 34 of file AxiStreamDmaV2Read.vhd.

◆ AXIS_READY_EN_G

AXIS_READY_EN_G boolean := false
Generic

Definition at line 35 of file AxiStreamDmaV2Read.vhd.

◆ AXIS_CONFIG_G

◆ AXI_CONFIG_G

Definition at line 37 of file AxiStreamDmaV2Read.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G natural := 1
Generic

Definition at line 38 of file AxiStreamDmaV2Read.vhd.

◆ BURST_BYTES_G

BURST_BYTES_G integer range 1 to 4096 := 4096
Generic

Definition at line 39 of file AxiStreamDmaV2Read.vhd.

◆ PEND_THRESH_G

PEND_THRESH_G natural := 0
Generic

Definition at line 40 of file AxiStreamDmaV2Read.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 43 of file AxiStreamDmaV2Read.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 44 of file AxiStreamDmaV2Read.vhd.

◆ dmaRdDescReq

Definition at line 46 of file AxiStreamDmaV2Read.vhd.

◆ dmaRdDescAck

dmaRdDescAck out sl
Port

Definition at line 47 of file AxiStreamDmaV2Read.vhd.

◆ dmaRdDescRet

Definition at line 48 of file AxiStreamDmaV2Read.vhd.

◆ dmaRdDescRetAck

Definition at line 49 of file AxiStreamDmaV2Read.vhd.

◆ dmaRdIdle

dmaRdIdle out sl
Port

Definition at line 51 of file AxiStreamDmaV2Read.vhd.

◆ axiCache

axiCache in slv ( 3 downto 0 )
Port

Definition at line 52 of file AxiStreamDmaV2Read.vhd.

◆ axisMaster

Definition at line 54 of file AxiStreamDmaV2Read.vhd.

◆ axisSlave

Definition at line 55 of file AxiStreamDmaV2Read.vhd.

◆ axisCtrl

Definition at line 56 of file AxiStreamDmaV2Read.vhd.

◆ axiReadMaster

Definition at line 58 of file AxiStreamDmaV2Read.vhd.

◆ axiReadSlave

Definition at line 59 of file AxiStreamDmaV2Read.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file AxiStreamDmaV2Read.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 21 of file AxiStreamDmaV2Read.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file AxiStreamDmaV2Read.vhd.

◆ std_logic_unsigned

Definition at line 23 of file AxiStreamDmaV2Read.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 25 of file AxiStreamDmaV2Read.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 26 of file AxiStreamDmaV2Read.vhd.

◆ AxiPkg

AxiPkg
Package

Definition at line 27 of file AxiStreamDmaV2Read.vhd.

◆ AxiDmaPkg

AxiDmaPkg
Package

Definition at line 28 of file AxiStreamDmaV2Read.vhd.


The documentation for this class was generated from the following file: