Inheritance diagram for AxiStreamDmaV2Desc:
Collaboration diagram for AxiStreamDmaV2Desc:
Entities | |
| rtl | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| NUMERIC_STD | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiPkg | Package <AxiPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
| AxiDmaPkg | Package <AxiDmaPkg> |
| ArbiterPkg | Package <ArbiterPkg> |
Generics | |
| TPD_G | time := 1 ns |
| CHAN_COUNT_G | integer range 1 to 16 := 1 |
| AXIL_BASE_ADDR_G | slv ( 31 downto 0 ) := x " 00000000 " |
| AXI_ERROR_RESP_G | slv ( 1 downto 0 ) := AXI_RESP_OK_C |
| AXI_READY_EN_G | boolean := false |
| AXI_CONFIG_G | AxiConfigType := AXI_CONFIG_INIT_C |
| DESC_AWIDTH_G | integer range 4 to 12 := 12 |
| ACK_WAIT_BVALID_G | boolean := true |
Ports | |
| axiClk | in sl |
| axiRst | in sl |
| axilReadMaster | in AxiLiteReadMasterType |
| axilReadSlave | out AxiLiteReadSlaveType |
| axilWriteMaster | in AxiLiteWriteMasterType |
| axilWriteSlave | out AxiLiteWriteSlaveType |
| interrupt | out sl |
| online | out slv ( CHAN_COUNT_G - 1 downto 0 ) |
| acknowledge | out slv ( CHAN_COUNT_G - 1 downto 0 ) |
| dmaWrDescReq | in AxiWriteDmaDescReqArray ( CHAN_COUNT_G - 1 downto 0 ) |
| dmaWrDescAck | out AxiWriteDmaDescAckArray ( CHAN_COUNT_G - 1 downto 0 ) |
| dmaWrDescRet | in AxiWriteDmaDescRetArray ( CHAN_COUNT_G - 1 downto 0 ) |
| dmaWrDescRetAck | out slv ( CHAN_COUNT_G - 1 downto 0 ) |
| dmaRdDescReq | out AxiReadDmaDescReqArray ( CHAN_COUNT_G - 1 downto 0 ) |
| dmaRdDescAck | in slv ( CHAN_COUNT_G - 1 downto 0 ) |
| dmaRdDescRet | in AxiReadDmaDescRetArray ( CHAN_COUNT_G - 1 downto 0 ) |
| dmaRdDescRetAck | out slv ( CHAN_COUNT_G - 1 downto 0 ) |
| axiCache | out slv ( 3 downto 0 ) |
| axiWriteMaster | out AxiWriteMasterType |
| axiWriteSlave | in AxiWriteSlaveType |
| axiWriteCtrl | in AxiCtrlType := AXI_CTRL_UNUSED_C |
Detailed Description
- See also
- entity
Definition at line 33 of file AxiStreamDmaV2Desc.vhd.
Member Data Documentation
◆ TPD_G
|
Generic |
Definition at line 35 of file AxiStreamDmaV2Desc.vhd.
◆ CHAN_COUNT_G
|
Generic |
Definition at line 36 of file AxiStreamDmaV2Desc.vhd.
◆ AXIL_BASE_ADDR_G
|
Generic |
Definition at line 37 of file AxiStreamDmaV2Desc.vhd.
◆ AXI_ERROR_RESP_G
|
Generic |
Definition at line 38 of file AxiStreamDmaV2Desc.vhd.
◆ AXI_READY_EN_G
|
Generic |
Definition at line 39 of file AxiStreamDmaV2Desc.vhd.
◆ AXI_CONFIG_G
|
Generic |
Definition at line 40 of file AxiStreamDmaV2Desc.vhd.
◆ DESC_AWIDTH_G
|
Generic |
Definition at line 41 of file AxiStreamDmaV2Desc.vhd.
◆ ACK_WAIT_BVALID_G
|
Generic |
Definition at line 42 of file AxiStreamDmaV2Desc.vhd.
◆ axiClk
Definition at line 45 of file AxiStreamDmaV2Desc.vhd.
◆ axiRst
Definition at line 46 of file AxiStreamDmaV2Desc.vhd.
◆ axilReadMaster
|
Port |
Definition at line 48 of file AxiStreamDmaV2Desc.vhd.
◆ axilReadSlave
|
Port |
Definition at line 49 of file AxiStreamDmaV2Desc.vhd.
◆ axilWriteMaster
Definition at line 50 of file AxiStreamDmaV2Desc.vhd.
◆ axilWriteSlave
|
Port |
Definition at line 51 of file AxiStreamDmaV2Desc.vhd.
◆ interrupt
Definition at line 53 of file AxiStreamDmaV2Desc.vhd.
◆ online
|
Port |
Definition at line 54 of file AxiStreamDmaV2Desc.vhd.
◆ acknowledge
|
Port |
Definition at line 55 of file AxiStreamDmaV2Desc.vhd.
◆ dmaWrDescReq
|
Port |
Definition at line 57 of file AxiStreamDmaV2Desc.vhd.
◆ dmaWrDescAck
|
Port |
Definition at line 58 of file AxiStreamDmaV2Desc.vhd.
◆ dmaWrDescRet
|
Port |
Definition at line 59 of file AxiStreamDmaV2Desc.vhd.
◆ dmaWrDescRetAck
|
Port |
Definition at line 60 of file AxiStreamDmaV2Desc.vhd.
◆ dmaRdDescReq
|
Port |
Definition at line 62 of file AxiStreamDmaV2Desc.vhd.
◆ dmaRdDescAck
|
Port |
Definition at line 63 of file AxiStreamDmaV2Desc.vhd.
◆ dmaRdDescRet
|
Port |
Definition at line 64 of file AxiStreamDmaV2Desc.vhd.
◆ dmaRdDescRetAck
|
Port |
Definition at line 65 of file AxiStreamDmaV2Desc.vhd.
◆ axiCache
Definition at line 67 of file AxiStreamDmaV2Desc.vhd.
◆ axiWriteMaster
|
Port |
Definition at line 69 of file AxiStreamDmaV2Desc.vhd.
◆ axiWriteSlave
|
Port |
Definition at line 70 of file AxiStreamDmaV2Desc.vhd.
◆ axiWriteCtrl
|
Port |
Definition at line 71 of file AxiStreamDmaV2Desc.vhd.
◆ ieee
|
Library |
Definition at line 19 of file AxiStreamDmaV2Desc.vhd.
◆ std_logic_1164
|
Package |
Definition at line 20 of file AxiStreamDmaV2Desc.vhd.
◆ std_logic_arith
|
Package |
Definition at line 21 of file AxiStreamDmaV2Desc.vhd.
◆ std_logic_unsigned
|
Package |
Definition at line 22 of file AxiStreamDmaV2Desc.vhd.
◆ NUMERIC_STD
|
Package |
Definition at line 23 of file AxiStreamDmaV2Desc.vhd.
◆ StdRtlPkg
|
Package |
Definition at line 25 of file AxiStreamDmaV2Desc.vhd.
◆ AxiPkg
|
Package |
Definition at line 26 of file AxiStreamDmaV2Desc.vhd.
◆ AxiLitePkg
|
Package |
Definition at line 27 of file AxiStreamDmaV2Desc.vhd.
◆ AxiDmaPkg
|
Package |
Definition at line 28 of file AxiStreamDmaV2Desc.vhd.
◆ ArbiterPkg
|
Package |
Definition at line 29 of file AxiStreamDmaV2Desc.vhd.
The documentation for this class was generated from the following file:
- axi/rtl/AxiStreamDmaV2Desc.vhd
