Inheritance diagram for AxiStreamDmaRingWrite:
Collaboration diagram for AxiStreamDmaRingWrite:
Entities | |
| rtl | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiStreamPkg | Package <AxiStreamPkg> |
| SsiPkg | Package <SsiPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
| AxiPkg | Package <AxiPkg> |
| AxiDmaPkg | Package <AxiDmaPkg> |
| AxiStreamDmaRingPkg | Package <AxiStreamDmaRingPkg> |
Generics | |
| TPD_G | time := 1 ns |
| BUFFERS_G | natural range 2 to 64 := 64 |
| BURST_SIZE_BYTES_G | natural range 4 to 2 ** 17 := 4096 |
| ENABLE_UNALIGN_G | boolean := false |
| TRIGGER_USER_BIT_G | natural range 0 to 7 := 2 |
| AXIL_BASE_ADDR_G | slv ( 31 downto 0 ) := ( others = > ' 0 ' ) |
| DATA_AXIS_CONFIG_G | AxiStreamConfigType := ssiAxiStreamConfig ( 8 ) |
| STATUS_AXIS_CONFIG_G | AxiStreamConfigType := ssiAxiStreamConfig ( 1 ) |
| AXI_WRITE_CONFIG_G | AxiConfigType := axiConfig ( 32 , 8 , 1 , 8 ) |
| BYP_SHIFT_G | boolean := true |
| BYP_CACHE_G | boolean := true |
Ports | |
| axilClk | in sl |
| axilRst | in sl |
| axilReadMaster | in AxiLiteReadMasterType |
| axilReadSlave | out AxiLiteReadSlaveType |
| axilWriteMaster | in AxiLiteWriteMasterType |
| axilWriteSlave | out AxiLiteWriteSlaveType |
| axisStatusClk | in sl |
| axisStatusRst | in sl |
| axisStatusMaster | out AxiStreamMasterType |
| axisStatusSlave | in AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C |
| axiClk | in sl |
| axiRst | in sl |
| axisDataMaster | in AxiStreamMasterType |
| axisDataSlave | out AxiStreamSlaveType |
| bufferClear | in slv ( log2 ( BUFFERS_G ) - 1 downto 0 ) := ( others = > ' 0 ' ) |
| bufferClearEn | in sl := ' 0 ' |
| bufferEnabled | out slv ( BUFFERS_G - 1 downto 0 ) |
| bufferEmpty | out slv ( BUFFERS_G - 1 downto 0 ) |
| bufferFull | out slv ( BUFFERS_G - 1 downto 0 ) |
| bufferDone | out slv ( BUFFERS_G - 1 downto 0 ) |
| bufferTriggered | out slv ( BUFFERS_G - 1 downto 0 ) |
| bufferError | out slv ( BUFFERS_G - 1 downto 0 ) |
| axiWriteMaster | out AxiWriteMasterType |
| axiWriteSlave | in AxiWriteSlaveType |
Detailed Description
- See also
- entity
Definition at line 33 of file AxiStreamDmaRingWrite.vhd.
Member Data Documentation
◆ TPD_G
|
Generic |
Definition at line 35 of file AxiStreamDmaRingWrite.vhd.
◆ BUFFERS_G
|
Generic |
Definition at line 36 of file AxiStreamDmaRingWrite.vhd.
◆ BURST_SIZE_BYTES_G
|
Generic |
Definition at line 37 of file AxiStreamDmaRingWrite.vhd.
◆ ENABLE_UNALIGN_G
|
Generic |
Definition at line 38 of file AxiStreamDmaRingWrite.vhd.
◆ TRIGGER_USER_BIT_G
|
Generic |
Definition at line 39 of file AxiStreamDmaRingWrite.vhd.
◆ AXIL_BASE_ADDR_G
|
Generic |
Definition at line 40 of file AxiStreamDmaRingWrite.vhd.
◆ DATA_AXIS_CONFIG_G
|
Generic |
Definition at line 41 of file AxiStreamDmaRingWrite.vhd.
◆ STATUS_AXIS_CONFIG_G
|
Generic |
Definition at line 42 of file AxiStreamDmaRingWrite.vhd.
◆ AXI_WRITE_CONFIG_G
|
Generic |
Definition at line 43 of file AxiStreamDmaRingWrite.vhd.
◆ BYP_SHIFT_G
|
Generic |
Definition at line 44 of file AxiStreamDmaRingWrite.vhd.
◆ BYP_CACHE_G
|
Generic |
Definition at line 45 of file AxiStreamDmaRingWrite.vhd.
◆ axilClk
Definition at line 48 of file AxiStreamDmaRingWrite.vhd.
◆ axilRst
Definition at line 49 of file AxiStreamDmaRingWrite.vhd.
◆ axilReadMaster
|
Port |
Definition at line 50 of file AxiStreamDmaRingWrite.vhd.
◆ axilReadSlave
|
Port |
Definition at line 51 of file AxiStreamDmaRingWrite.vhd.
◆ axilWriteMaster
Definition at line 52 of file AxiStreamDmaRingWrite.vhd.
◆ axilWriteSlave
|
Port |
Definition at line 53 of file AxiStreamDmaRingWrite.vhd.
◆ axisStatusClk
|
Port |
Definition at line 56 of file AxiStreamDmaRingWrite.vhd.
◆ axisStatusRst
|
Port |
Definition at line 57 of file AxiStreamDmaRingWrite.vhd.
◆ axisStatusMaster
|
Port |
Definition at line 58 of file AxiStreamDmaRingWrite.vhd.
◆ axisStatusSlave
Definition at line 59 of file AxiStreamDmaRingWrite.vhd.
◆ axiClk
Definition at line 62 of file AxiStreamDmaRingWrite.vhd.
◆ axiRst
Definition at line 63 of file AxiStreamDmaRingWrite.vhd.
◆ axisDataMaster
|
Port |
Definition at line 65 of file AxiStreamDmaRingWrite.vhd.
◆ axisDataSlave
|
Port |
Definition at line 66 of file AxiStreamDmaRingWrite.vhd.
◆ bufferClear
|
Port |
Definition at line 68 of file AxiStreamDmaRingWrite.vhd.
◆ bufferClearEn
|
Port |
Definition at line 69 of file AxiStreamDmaRingWrite.vhd.
◆ bufferEnabled
|
Port |
Definition at line 70 of file AxiStreamDmaRingWrite.vhd.
◆ bufferEmpty
|
Port |
Definition at line 71 of file AxiStreamDmaRingWrite.vhd.
◆ bufferFull
|
Port |
Definition at line 72 of file AxiStreamDmaRingWrite.vhd.
◆ bufferDone
|
Port |
Definition at line 73 of file AxiStreamDmaRingWrite.vhd.
◆ bufferTriggered
|
Port |
Definition at line 74 of file AxiStreamDmaRingWrite.vhd.
◆ bufferError
|
Port |
Definition at line 75 of file AxiStreamDmaRingWrite.vhd.
◆ axiWriteMaster
|
Port |
Definition at line 78 of file AxiStreamDmaRingWrite.vhd.
◆ axiWriteSlave
|
Port |
Definition at line 79 of file AxiStreamDmaRingWrite.vhd.
◆ ieee
|
Library |
Definition at line 18 of file AxiStreamDmaRingWrite.vhd.
◆ std_logic_1164
|
Package |
Definition at line 19 of file AxiStreamDmaRingWrite.vhd.
◆ std_logic_unsigned
|
Package |
Definition at line 20 of file AxiStreamDmaRingWrite.vhd.
◆ std_logic_arith
|
Package |
Definition at line 21 of file AxiStreamDmaRingWrite.vhd.
◆ StdRtlPkg
|
Package |
Definition at line 23 of file AxiStreamDmaRingWrite.vhd.
◆ AxiStreamPkg
|
Package |
Definition at line 24 of file AxiStreamDmaRingWrite.vhd.
◆ SsiPkg
|
Package |
Definition at line 25 of file AxiStreamDmaRingWrite.vhd.
◆ AxiLitePkg
|
Package |
Definition at line 26 of file AxiStreamDmaRingWrite.vhd.
◆ AxiPkg
|
Package |
Definition at line 27 of file AxiStreamDmaRingWrite.vhd.
◆ AxiDmaPkg
|
Package |
Definition at line 28 of file AxiStreamDmaRingWrite.vhd.
◆ AxiStreamDmaRingPkg
|
Package |
Definition at line 29 of file AxiStreamDmaRingWrite.vhd.
The documentation for this class was generated from the following file:
- axi/rtl/AxiStreamDmaRingWrite.vhd
