SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiStreamDmaRingRead Entity Reference
axi
+ Inheritance diagram for AxiStreamDmaRingRead:
+ Collaboration diagram for AxiStreamDmaRingRead:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiLiteMasterPkg  Package <AxiLiteMasterPkg>
AxiPkg  Package <AxiPkg>
AxiDmaPkg  Package <AxiDmaPkg>
AxiStreamDmaRingPkg  Package <AxiStreamDmaRingPkg>

Generics

TPD_G  time := 1 ns
BUFFERS_G  natural range 2 to 64 := 64
BURST_SIZE_BYTES_G  natural range 4 to 2 ** 17 := 4096
SSI_OUTPUT_G  boolean := false
AXIL_BASE_ADDR_G  slv ( 31 downto 0 ) := ( others = > ' 0 ' )
AXI_STREAM_READY_EN_G  boolean := true
AXI_STREAM_CONFIG_G  AxiStreamConfigType := ssiAxiStreamConfig ( 8 )
AXI_READ_CONFIG_G  AxiConfigType := axiConfig ( 32 , 8 , 1 , 8 )

Ports

axilClk   in sl
axilRst   in sl
axilReadMaster   out AxiLiteReadMasterType
axilReadSlave   in AxiLiteReadSlaveType
axilWriteMaster   out AxiLiteWriteMasterType
axilWriteSlave   in AxiLiteWriteSlaveType
statusClk   in sl
statusRst   in sl
statusMaster   in AxiStreamMasterType
statusSlave   out AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
dataMaster   out AxiStreamMasterType
dataSlave   in AxiStreamSlaveType
dataCtrl   in AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C
axiClk   in sl
axiRst   in sl
axiReadMaster   out AxiReadMasterType
axiReadSlave   in AxiReadSlaveType

Detailed Description

See also
entity

Definition at line 34 of file AxiStreamDmaRingRead.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 37 of file AxiStreamDmaRingRead.vhd.

◆ BUFFERS_G

BUFFERS_G natural range 2 to 64 := 64
Generic

Definition at line 38 of file AxiStreamDmaRingRead.vhd.

◆ BURST_SIZE_BYTES_G

BURST_SIZE_BYTES_G natural range 4 to 2 ** 17 := 4096
Generic

Definition at line 39 of file AxiStreamDmaRingRead.vhd.

◆ SSI_OUTPUT_G

SSI_OUTPUT_G boolean := false
Generic

Definition at line 40 of file AxiStreamDmaRingRead.vhd.

◆ AXIL_BASE_ADDR_G

AXIL_BASE_ADDR_G slv ( 31 downto 0 ) := ( others = > ' 0 ' )
Generic

Definition at line 41 of file AxiStreamDmaRingRead.vhd.

◆ AXI_STREAM_READY_EN_G

AXI_STREAM_READY_EN_G boolean := true
Generic

Definition at line 42 of file AxiStreamDmaRingRead.vhd.

◆ AXI_STREAM_CONFIG_G

AXI_STREAM_CONFIG_G AxiStreamConfigType := ssiAxiStreamConfig ( 8 )
Generic

Definition at line 43 of file AxiStreamDmaRingRead.vhd.

◆ AXI_READ_CONFIG_G

AXI_READ_CONFIG_G AxiConfigType := axiConfig ( 32 , 8 , 1 , 8 )
Generic

Definition at line 44 of file AxiStreamDmaRingRead.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 47 of file AxiStreamDmaRingRead.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 48 of file AxiStreamDmaRingRead.vhd.

◆ axilReadMaster

axilReadMaster out AxiLiteReadMasterType
Port

Definition at line 49 of file AxiStreamDmaRingRead.vhd.

◆ axilReadSlave

axilReadSlave in AxiLiteReadSlaveType
Port

Definition at line 50 of file AxiStreamDmaRingRead.vhd.

◆ axilWriteMaster

axilWriteMaster out AxiLiteWriteMasterType
Port

Definition at line 51 of file AxiStreamDmaRingRead.vhd.

◆ axilWriteSlave

axilWriteSlave in AxiLiteWriteSlaveType
Port

Definition at line 52 of file AxiStreamDmaRingRead.vhd.

◆ statusClk

statusClk in sl
Port

Definition at line 55 of file AxiStreamDmaRingRead.vhd.

◆ statusRst

statusRst in sl
Port

Definition at line 56 of file AxiStreamDmaRingRead.vhd.

◆ statusMaster

statusMaster in AxiStreamMasterType
Port

Definition at line 57 of file AxiStreamDmaRingRead.vhd.

◆ statusSlave

statusSlave out AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
Port

Definition at line 58 of file AxiStreamDmaRingRead.vhd.

◆ dataMaster

dataMaster out AxiStreamMasterType
Port

Definition at line 63 of file AxiStreamDmaRingRead.vhd.

◆ dataSlave

dataSlave in AxiStreamSlaveType
Port

Definition at line 64 of file AxiStreamDmaRingRead.vhd.

◆ dataCtrl

dataCtrl in AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C
Port

Definition at line 65 of file AxiStreamDmaRingRead.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 68 of file AxiStreamDmaRingRead.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 69 of file AxiStreamDmaRingRead.vhd.

◆ axiReadMaster

axiReadMaster out AxiReadMasterType
Port

Definition at line 70 of file AxiStreamDmaRingRead.vhd.

◆ axiReadSlave

axiReadSlave in AxiReadSlaveType
Port

Definition at line 71 of file AxiStreamDmaRingRead.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiStreamDmaRingRead.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiStreamDmaRingRead.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiStreamDmaRingRead.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiStreamDmaRingRead.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiStreamDmaRingRead.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 24 of file AxiStreamDmaRingRead.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 25 of file AxiStreamDmaRingRead.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 26 of file AxiStreamDmaRingRead.vhd.

◆ AxiLiteMasterPkg

AxiLiteMasterPkg
Package

Definition at line 27 of file AxiStreamDmaRingRead.vhd.

◆ AxiPkg

AxiPkg
Package

Definition at line 28 of file AxiStreamDmaRingRead.vhd.

◆ AxiDmaPkg

AxiDmaPkg
Package

Definition at line 29 of file AxiStreamDmaRingRead.vhd.

◆ AxiStreamDmaRingPkg

AxiStreamDmaRingPkg
Package

Definition at line 30 of file AxiStreamDmaRingRead.vhd.

The documentation for this class was generated from the following file: