SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiSpiMaster Entity Reference
protocols » spi
+ Inheritance diagram for AxiSpiMaster:
+ Collaboration diagram for AxiSpiMaster:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
vcomponents 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
ADDRESS_SIZE_G  natural := 15
DATA_SIZE_G  natural := 8
MODE_G  string := " RW "
CPHA_G  sl := ' 0 '
CPOL_G  sl := ' 0 '
CLK_PERIOD_G  real := 6 . 4E - 9
SPI_SCLK_PERIOD_G  real := 100 . 0E - 6
SPI_NUM_CHIPS_G  positive := 1

Ports

axiClk   in sl
axiRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
coreSclk   out sl
coreSDin   in sl
coreSDout   out sl
coreCsb   out sl
coreMCsb   out slv ( SPI_NUM_CHIPS_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 40 of file AxiSpiMaster.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 42 of file AxiSpiMaster.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 43 of file AxiSpiMaster.vhd.

◆ ADDRESS_SIZE_G

ADDRESS_SIZE_G natural := 15
Generic

Definition at line 44 of file AxiSpiMaster.vhd.

◆ DATA_SIZE_G

DATA_SIZE_G natural := 8
Generic

Definition at line 45 of file AxiSpiMaster.vhd.

◆ MODE_G

MODE_G string := " RW "
Generic

Definition at line 46 of file AxiSpiMaster.vhd.

◆ CPHA_G

CPHA_G sl := ' 0 '
Generic

Definition at line 47 of file AxiSpiMaster.vhd.

◆ CPOL_G

CPOL_G sl := ' 0 '
Generic

Definition at line 48 of file AxiSpiMaster.vhd.

◆ CLK_PERIOD_G

CLK_PERIOD_G real := 6 . 4E - 9
Generic

Definition at line 49 of file AxiSpiMaster.vhd.

◆ SPI_SCLK_PERIOD_G

SPI_SCLK_PERIOD_G real := 100 . 0E - 6
Generic

Definition at line 50 of file AxiSpiMaster.vhd.

◆ SPI_NUM_CHIPS_G

SPI_NUM_CHIPS_G positive := 1
Generic

Definition at line 52 of file AxiSpiMaster.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 54 of file AxiSpiMaster.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 55 of file AxiSpiMaster.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 57 of file AxiSpiMaster.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 58 of file AxiSpiMaster.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 59 of file AxiSpiMaster.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 60 of file AxiSpiMaster.vhd.

◆ coreSclk

coreSclk out sl
Port

Definition at line 62 of file AxiSpiMaster.vhd.

◆ coreSDin

coreSDin in sl
Port

Definition at line 63 of file AxiSpiMaster.vhd.

◆ coreSDout

coreSDout out sl
Port

Definition at line 64 of file AxiSpiMaster.vhd.

◆ coreCsb

coreCsb out sl
Port

Definition at line 65 of file AxiSpiMaster.vhd.

◆ coreMCsb

coreMCsb out slv ( SPI_NUM_CHIPS_G - 1 downto 0 )
Port

Definition at line 67 of file AxiSpiMaster.vhd.

◆ ieee

ieee
Library

Definition at line 27 of file AxiSpiMaster.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 28 of file AxiSpiMaster.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 29 of file AxiSpiMaster.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 30 of file AxiSpiMaster.vhd.

◆ unisim

unisim
Library

Definition at line 32 of file AxiSpiMaster.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 33 of file AxiSpiMaster.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 35 of file AxiSpiMaster.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 36 of file AxiSpiMaster.vhd.

The documentation for this class was generated from the following file: