SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiReadPathFifo Entity Reference
axi
+ Inheritance diagram for AxiReadPathFifo:
+ Collaboration diagram for AxiReadPathFifo:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiPkg  Package <AxiPkg>

Generics

TPD_G  time := 1 ns
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
GEN_SYNC_FIFO_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
ADDR_LSB_G  natural range 0 to 31 := 0
ID_FIXED_EN_G  boolean := false
SIZE_FIXED_EN_G  boolean := false
BURST_FIXED_EN_G  boolean := false
LEN_FIXED_EN_G  boolean := false
LOCK_FIXED_EN_G  boolean := false
PROT_FIXED_EN_G  boolean := false
CACHE_FIXED_EN_G  boolean := false
ADDR_BRAM_EN_G  boolean := true
ADDR_CASCADE_SIZE_G  integer range 1 to ( 2 ** 24 ) := 1
ADDR_FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 9
DATA_BRAM_EN_G  boolean := true
DATA_CASCADE_SIZE_G  integer range 1 to ( 2 ** 24 ) := 1
DATA_FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 9
AXI_CONFIG_G  AxiConfigType := AXI_CONFIG_INIT_C

Ports

sAxiClk   in sl
sAxiRst   in sl
sAxiReadMaster   in AxiReadMasterType
sAxiReadSlave   out AxiReadSlaveType
mAxiClk   in sl
mAxiRst   in sl
mAxiReadMaster   out AxiReadMasterType
mAxiReadSlave   in AxiReadSlaveType

Detailed Description

See also
entity

Definition at line 28 of file AxiReadPathFifo.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file AxiReadPathFifo.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 35 of file AxiReadPathFifo.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 36 of file AxiReadPathFifo.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 37 of file AxiReadPathFifo.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 38 of file AxiReadPathFifo.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 39 of file AxiReadPathFifo.vhd.

◆ ADDR_LSB_G

ADDR_LSB_G natural range 0 to 31 := 0
Generic

Definition at line 42 of file AxiReadPathFifo.vhd.

◆ ID_FIXED_EN_G

ID_FIXED_EN_G boolean := false
Generic

Definition at line 43 of file AxiReadPathFifo.vhd.

◆ SIZE_FIXED_EN_G

SIZE_FIXED_EN_G boolean := false
Generic

Definition at line 44 of file AxiReadPathFifo.vhd.

◆ BURST_FIXED_EN_G

BURST_FIXED_EN_G boolean := false
Generic

Definition at line 45 of file AxiReadPathFifo.vhd.

◆ LEN_FIXED_EN_G

LEN_FIXED_EN_G boolean := false
Generic

Definition at line 46 of file AxiReadPathFifo.vhd.

◆ LOCK_FIXED_EN_G

LOCK_FIXED_EN_G boolean := false
Generic

Definition at line 47 of file AxiReadPathFifo.vhd.

◆ PROT_FIXED_EN_G

PROT_FIXED_EN_G boolean := false
Generic

Definition at line 48 of file AxiReadPathFifo.vhd.

◆ CACHE_FIXED_EN_G

CACHE_FIXED_EN_G boolean := false
Generic

Definition at line 49 of file AxiReadPathFifo.vhd.

◆ ADDR_BRAM_EN_G

ADDR_BRAM_EN_G boolean := true
Generic

Definition at line 52 of file AxiReadPathFifo.vhd.

◆ ADDR_CASCADE_SIZE_G

ADDR_CASCADE_SIZE_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 53 of file AxiReadPathFifo.vhd.

◆ ADDR_FIFO_ADDR_WIDTH_G

ADDR_FIFO_ADDR_WIDTH_G integer range 4 to 48 := 9
Generic

Definition at line 54 of file AxiReadPathFifo.vhd.

◆ DATA_BRAM_EN_G

DATA_BRAM_EN_G boolean := true
Generic

Definition at line 57 of file AxiReadPathFifo.vhd.

◆ DATA_CASCADE_SIZE_G

DATA_CASCADE_SIZE_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 58 of file AxiReadPathFifo.vhd.

◆ DATA_FIFO_ADDR_WIDTH_G

DATA_FIFO_ADDR_WIDTH_G integer range 4 to 48 := 9
Generic

Definition at line 59 of file AxiReadPathFifo.vhd.

◆ AXI_CONFIG_G

AXI_CONFIG_G AxiConfigType := AXI_CONFIG_INIT_C
Generic

Definition at line 63 of file AxiReadPathFifo.vhd.

◆ sAxiClk

sAxiClk in sl
Port

Definition at line 67 of file AxiReadPathFifo.vhd.

◆ sAxiRst

sAxiRst in sl
Port

Definition at line 68 of file AxiReadPathFifo.vhd.

◆ sAxiReadMaster

sAxiReadMaster in AxiReadMasterType
Port

Definition at line 69 of file AxiReadPathFifo.vhd.

◆ sAxiReadSlave

sAxiReadSlave out AxiReadSlaveType
Port

Definition at line 70 of file AxiReadPathFifo.vhd.

◆ mAxiClk

mAxiClk in sl
Port

Definition at line 73 of file AxiReadPathFifo.vhd.

◆ mAxiRst

mAxiRst in sl
Port

Definition at line 74 of file AxiReadPathFifo.vhd.

◆ mAxiReadMaster

mAxiReadMaster out AxiReadMasterType
Port

Definition at line 75 of file AxiReadPathFifo.vhd.

◆ mAxiReadSlave

mAxiReadSlave in AxiReadSlaveType
Port

Definition at line 76 of file AxiReadPathFifo.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiReadPathFifo.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiReadPathFifo.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiReadPathFifo.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiReadPathFifo.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiReadPathFifo.vhd.

◆ AxiPkg

AxiPkg
Package

Definition at line 24 of file AxiReadPathFifo.vhd.

The documentation for this class was generated from the following file: