SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiMicronP30Reg Entity Reference
devices » Micron » p30
+ Inheritance diagram for AxiMicronP30Reg:
+ Collaboration diagram for AxiMicronP30Reg:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
vcomponents 

Generics

TPD_G  time := 1 ns
MEM_ADDR_MASK_G  slv ( 31 downto 0 ) := x " 00000000 "
AXI_CLK_FREQ_G  real := 200 . 0E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

flashAddr   out slv ( 30 downto 0 )
flashAdv   out sl
flashClk   out sl
flashRstL   out sl
flashCeL   out sl
flashOeL   out sl
flashWeL   out sl
flashTri   out sl
flashDin   out slv ( 15 downto 0 )
flashDout   in slv ( 15 downto 0 )
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl

Detailed Description

See also
entity

Definition at line 31 of file AxiMicronP30Reg.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file AxiMicronP30Reg.vhd.

◆ MEM_ADDR_MASK_G

MEM_ADDR_MASK_G slv ( 31 downto 0 ) := x " 00000000 "
Generic

Definition at line 34 of file AxiMicronP30Reg.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 35 of file AxiMicronP30Reg.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 36 of file AxiMicronP30Reg.vhd.

◆ flashAddr

flashAddr out slv ( 30 downto 0 )
Port

Definition at line 39 of file AxiMicronP30Reg.vhd.

◆ flashAdv

flashAdv out sl
Port

Definition at line 40 of file AxiMicronP30Reg.vhd.

◆ flashClk

flashClk out sl
Port

Definition at line 41 of file AxiMicronP30Reg.vhd.

◆ flashRstL

flashRstL out sl
Port

Definition at line 42 of file AxiMicronP30Reg.vhd.

◆ flashCeL

flashCeL out sl
Port

Definition at line 43 of file AxiMicronP30Reg.vhd.

◆ flashOeL

flashOeL out sl
Port

Definition at line 44 of file AxiMicronP30Reg.vhd.

◆ flashWeL

flashWeL out sl
Port

Definition at line 45 of file AxiMicronP30Reg.vhd.

◆ flashTri

flashTri out sl
Port

Definition at line 46 of file AxiMicronP30Reg.vhd.

◆ flashDin

flashDin out slv ( 15 downto 0 )
Port

Definition at line 47 of file AxiMicronP30Reg.vhd.

◆ flashDout

flashDout in slv ( 15 downto 0 )
Port

Definition at line 48 of file AxiMicronP30Reg.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 50 of file AxiMicronP30Reg.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 51 of file AxiMicronP30Reg.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 52 of file AxiMicronP30Reg.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 53 of file AxiMicronP30Reg.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 55 of file AxiMicronP30Reg.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 56 of file AxiMicronP30Reg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiMicronP30Reg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiMicronP30Reg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiMicronP30Reg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiMicronP30Reg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiMicronP30Reg.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiMicronP30Reg.vhd.

◆ unisim

unisim
Library

Definition at line 26 of file AxiMicronP30Reg.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 27 of file AxiMicronP30Reg.vhd.

The documentation for this class was generated from the following file: