SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiMicronP30Core Entity Reference
devices » Micron » p30
+ Inheritance diagram for AxiMicronP30Core:
+ Collaboration diagram for AxiMicronP30Core:

Entities

mapping  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiMicronP30Pkg  Package <AxiMicronP30Pkg>
vcomponents 

Generics

TPD_G  time := 1 ns
MEM_ADDR_MASK_G  slv ( 31 downto 0 ) := x " 00000000 "
AXI_CLK_FREQ_G  real := 200 . 0E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

flashIn   in AxiMicronP30InType
flashInOut   inout AxiMicronP30InOutType
flashOut   out AxiMicronP30OutType
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl

Detailed Description

See also
entity

Definition at line 30 of file AxiMicronP30Core.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file AxiMicronP30Core.vhd.

◆ MEM_ADDR_MASK_G

MEM_ADDR_MASK_G slv ( 31 downto 0 ) := x " 00000000 "
Generic

Definition at line 33 of file AxiMicronP30Core.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 34 of file AxiMicronP30Core.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 35 of file AxiMicronP30Core.vhd.

◆ flashIn

flashIn in AxiMicronP30InType
Port

Definition at line 38 of file AxiMicronP30Core.vhd.

◆ flashInOut

flashInOut inout AxiMicronP30InOutType
Port

Definition at line 39 of file AxiMicronP30Core.vhd.

◆ flashOut

flashOut out AxiMicronP30OutType
Port

Definition at line 40 of file AxiMicronP30Core.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 42 of file AxiMicronP30Core.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 43 of file AxiMicronP30Core.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 44 of file AxiMicronP30Core.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 45 of file AxiMicronP30Core.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 47 of file AxiMicronP30Core.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 48 of file AxiMicronP30Core.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiMicronP30Core.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiMicronP30Core.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file AxiMicronP30Core.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 22 of file AxiMicronP30Core.vhd.

◆ AxiMicronP30Pkg

AxiMicronP30Pkg
Package

Definition at line 23 of file AxiMicronP30Core.vhd.

◆ unisim

unisim
Library

Definition at line 25 of file AxiMicronP30Core.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 26 of file AxiMicronP30Core.vhd.

The documentation for this class was generated from the following file: