SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiMicronN25QReg Entity Reference
devices » Micron » n25q
+ Inheritance diagram for AxiMicronN25QReg:
+ Collaboration diagram for AxiMicronN25QReg:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
MEM_ADDR_MASK_G  slv ( 31 downto 0 ) := x " 00000000 "
AXI_CLK_FREQ_G  real := 200 . 0E + 6
SPI_CLK_FREQ_G  real := 25 . 0E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

csL   out sl
sck   out sl
mosi   out sl
miso   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl

Detailed Description

See also
entity

Definition at line 28 of file AxiMicronN25QReg.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file AxiMicronN25QReg.vhd.

◆ MEM_ADDR_MASK_G

MEM_ADDR_MASK_G slv ( 31 downto 0 ) := x " 00000000 "
Generic

Definition at line 31 of file AxiMicronN25QReg.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 32 of file AxiMicronN25QReg.vhd.

◆ SPI_CLK_FREQ_G

SPI_CLK_FREQ_G real := 25 . 0E + 6
Generic

Definition at line 33 of file AxiMicronN25QReg.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 34 of file AxiMicronN25QReg.vhd.

◆ csL

csL out sl
Port

Definition at line 37 of file AxiMicronN25QReg.vhd.

◆ sck

sck out sl
Port

Definition at line 38 of file AxiMicronN25QReg.vhd.

◆ mosi

mosi out sl
Port

Definition at line 39 of file AxiMicronN25QReg.vhd.

◆ miso

miso in sl
Port

Definition at line 40 of file AxiMicronN25QReg.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 42 of file AxiMicronN25QReg.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 43 of file AxiMicronN25QReg.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 44 of file AxiMicronN25QReg.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 45 of file AxiMicronN25QReg.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 47 of file AxiMicronN25QReg.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 48 of file AxiMicronN25QReg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiMicronN25QReg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiMicronN25QReg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiMicronN25QReg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiMicronN25QReg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiMicronN25QReg.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiMicronN25QReg.vhd.

The documentation for this class was generated from the following file: