SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiMicronN25QCore Entity Reference
devices » Micron » n25q
+ Inheritance diagram for AxiMicronN25QCore:
+ Collaboration diagram for AxiMicronN25QCore:

Entities

mapping  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
vcomponents 

Generics

TPD_G  time := 1 ns
MEM_ADDR_MASK_G  slv ( 31 downto 0 ) := x " 00000000 "
AXI_CLK_FREQ_G  real := 200 . 0E + 6
SPI_CLK_FREQ_G  real := 25 . 0E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

csL   out sl
sck   out sl
mosi   out sl
miso   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl

Detailed Description

See also
entity

Definition at line 31 of file AxiMicronN25QCore.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file AxiMicronN25QCore.vhd.

◆ MEM_ADDR_MASK_G

MEM_ADDR_MASK_G slv ( 31 downto 0 ) := x " 00000000 "
Generic

Definition at line 34 of file AxiMicronN25QCore.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 35 of file AxiMicronN25QCore.vhd.

◆ SPI_CLK_FREQ_G

SPI_CLK_FREQ_G real := 25 . 0E + 6
Generic

Definition at line 36 of file AxiMicronN25QCore.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 37 of file AxiMicronN25QCore.vhd.

◆ csL

csL out sl
Port

Definition at line 40 of file AxiMicronN25QCore.vhd.

◆ sck

sck out sl
Port

Definition at line 41 of file AxiMicronN25QCore.vhd.

◆ mosi

mosi out sl
Port

Definition at line 42 of file AxiMicronN25QCore.vhd.

◆ miso

miso in sl
Port

Definition at line 43 of file AxiMicronN25QCore.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 45 of file AxiMicronN25QCore.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 46 of file AxiMicronN25QCore.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 47 of file AxiMicronN25QCore.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 48 of file AxiMicronN25QCore.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 50 of file AxiMicronN25QCore.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 51 of file AxiMicronN25QCore.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file AxiMicronN25QCore.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 21 of file AxiMicronN25QCore.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiMicronN25QCore.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiMicronN25QCore.vhd.

◆ unisim

unisim
Library

Definition at line 26 of file AxiMicronN25QCore.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 27 of file AxiMicronN25QCore.vhd.

The documentation for this class was generated from the following file: