SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiMemTester Entity Reference
axi
+ Inheritance diagram for AxiMemTester:
+ Collaboration diagram for AxiMemTester:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiPkg  Package <AxiPkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
START_ADDR_G  slv := X " 00000000 "
STOP_ADDR_G  slv := X " FFFFFFFF "
BURST_LEN_G  positive range 1 to 4096 := 4096
AXI_CONFIG_G  AxiConfigType := AXI_CONFIG_INIT_C

Ports

axilClk   in sl
axilRst   in sl
axilReadMaster   in AxiLiteReadMasterType
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType
axilWriteSlave   out AxiLiteWriteSlaveType
memReady   out sl
memError   out sl
axiClk   in sl
axiRst   in sl
start   in sl
axiWriteMaster   out AxiWriteMasterType
axiWriteSlave   in AxiWriteSlaveType
axiReadMaster   out AxiReadMasterType
axiReadSlave   in AxiReadSlaveType

Detailed Description

See also
entity

Definition at line 29 of file AxiMemTester.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file AxiMemTester.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 32 of file AxiMemTester.vhd.

◆ START_ADDR_G

START_ADDR_G slv := X " 00000000 "
Generic

Definition at line 33 of file AxiMemTester.vhd.

◆ STOP_ADDR_G

STOP_ADDR_G slv := X " FFFFFFFF "
Generic

Definition at line 34 of file AxiMemTester.vhd.

◆ BURST_LEN_G

BURST_LEN_G positive range 1 to 4096 := 4096
Generic

Definition at line 35 of file AxiMemTester.vhd.

◆ AXI_CONFIG_G

AXI_CONFIG_G AxiConfigType := AXI_CONFIG_INIT_C
Generic

Definition at line 36 of file AxiMemTester.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 39 of file AxiMemTester.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 40 of file AxiMemTester.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType
Port

Definition at line 41 of file AxiMemTester.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 42 of file AxiMemTester.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 43 of file AxiMemTester.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 44 of file AxiMemTester.vhd.

◆ memReady

memReady out sl
Port

Definition at line 45 of file AxiMemTester.vhd.

◆ memError

memError out sl
Port

Definition at line 46 of file AxiMemTester.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 48 of file AxiMemTester.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 49 of file AxiMemTester.vhd.

◆ start

start in sl
Port

Definition at line 50 of file AxiMemTester.vhd.

◆ axiWriteMaster

axiWriteMaster out AxiWriteMasterType
Port

Definition at line 51 of file AxiMemTester.vhd.

◆ axiWriteSlave

axiWriteSlave in AxiWriteSlaveType
Port

Definition at line 52 of file AxiMemTester.vhd.

◆ axiReadMaster

axiReadMaster out AxiReadMasterType
Port

Definition at line 53 of file AxiMemTester.vhd.

◆ axiReadSlave

axiReadSlave in AxiReadSlaveType
Port

Definition at line 54 of file AxiMemTester.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiMemTester.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiMemTester.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file AxiMemTester.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file AxiMemTester.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiMemTester.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiMemTester.vhd.

◆ AxiPkg

AxiPkg
Package

Definition at line 25 of file AxiMemTester.vhd.

The documentation for this class was generated from the following file: