SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiLtc2270Reg Entity Reference
devices » Linear » lct2270
+ Inheritance diagram for AxiLtc2270Reg:
+ Collaboration diagram for AxiLtc2270Reg:

Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiLtc2270Pkg  Package <AxiLtc2270Pkg>
vcomponents 

Generics

TPD_G  time := 1 ns
DMODE_INIT_G  slv ( 1 downto 0 ) := " 00 "
DELAY_INIT_G  Slv5VectorArray ( 0 to 1 , 0 to 7 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
STATUS_CNT_WIDTH_G  natural range 1 to 32 := 32
AXI_CLK_FREQ_G  real := 200 . 0E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

adcCs   out sl
adcSck   out sl
adcSdi   out sl
adcSdo   inout sl
adcPar   out sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
status   in AxiLtc2270StatusType
config   out AxiLtc2270ConfigType
axiClk   in sl
axiRst   in sl
refClk200MHz   in sl

Detailed Description

See also
entity

Definition at line 32 of file AxiLtc2270Reg.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 34 of file AxiLtc2270Reg.vhd.

◆ DMODE_INIT_G

DMODE_INIT_G slv ( 1 downto 0 ) := " 00 "
Generic

Definition at line 35 of file AxiLtc2270Reg.vhd.

◆ DELAY_INIT_G

DELAY_INIT_G Slv5VectorArray ( 0 to 1 , 0 to 7 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
Generic

Definition at line 36 of file AxiLtc2270Reg.vhd.

◆ STATUS_CNT_WIDTH_G

STATUS_CNT_WIDTH_G natural range 1 to 32 := 32
Generic

Definition at line 37 of file AxiLtc2270Reg.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 38 of file AxiLtc2270Reg.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 39 of file AxiLtc2270Reg.vhd.

◆ adcCs

adcCs out sl
Port

Definition at line 42 of file AxiLtc2270Reg.vhd.

◆ adcSck

adcSck out sl
Port

Definition at line 43 of file AxiLtc2270Reg.vhd.

◆ adcSdi

adcSdi out sl
Port

Definition at line 44 of file AxiLtc2270Reg.vhd.

◆ adcSdo

adcSdo inout sl
Port

Definition at line 45 of file AxiLtc2270Reg.vhd.

◆ adcPar

adcPar out sl
Port

Definition at line 46 of file AxiLtc2270Reg.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 48 of file AxiLtc2270Reg.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 49 of file AxiLtc2270Reg.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 50 of file AxiLtc2270Reg.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 51 of file AxiLtc2270Reg.vhd.

◆ status

status in AxiLtc2270StatusType
Port

Definition at line 53 of file AxiLtc2270Reg.vhd.

◆ config

config out AxiLtc2270ConfigType
Port

Definition at line 54 of file AxiLtc2270Reg.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 56 of file AxiLtc2270Reg.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 57 of file AxiLtc2270Reg.vhd.

◆ refClk200MHz

refClk200MHz in sl
Port

Definition at line 58 of file AxiLtc2270Reg.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiLtc2270Reg.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiLtc2270Reg.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiLtc2270Reg.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiLtc2270Reg.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiLtc2270Reg.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiLtc2270Reg.vhd.

◆ AxiLtc2270Pkg

AxiLtc2270Pkg
Package

Definition at line 25 of file AxiLtc2270Reg.vhd.

◆ unisim

unisim
Library

Definition at line 27 of file AxiLtc2270Reg.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 28 of file AxiLtc2270Reg.vhd.

The documentation for this class was generated from the following file: