SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiLtc2270Core Entity Reference
devices » Linear » lct2270
+ Inheritance diagram for AxiLtc2270Core:
+ Collaboration diagram for AxiLtc2270Core:

Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiLtc2270Pkg  Package <AxiLtc2270Pkg>

Generics

TPD_G  time := 1 ns
DMODE_INIT_G  slv ( 1 downto 0 ) := " 00 "
DELAY_INIT_G  Slv5VectorArray ( 0 to 1 , 0 to 7 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
IODELAY_GROUP_G  string := " AXI_LTC2270_IODELAY_GRP "
STATUS_CNT_WIDTH_G  natural range 1 to 32 := 32
AXI_CLK_FREQ_G  real := 200 . 0E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

adcIn   in AxiLtc2270InType
adcOut   out AxiLtc2270OutType
adcInOut   inout AxiLtc2270InOutType
adcValid   out slv ( 0 to 1 )
adcData   out Slv16Array ( 0 to 1 )
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl
adcClk   in sl
refclk200MHz   in sl

Detailed Description

See also
entity

Definition at line 28 of file AxiLtc2270Core.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file AxiLtc2270Core.vhd.

◆ DMODE_INIT_G

DMODE_INIT_G slv ( 1 downto 0 ) := " 00 "
Generic

Definition at line 31 of file AxiLtc2270Core.vhd.

◆ DELAY_INIT_G

DELAY_INIT_G Slv5VectorArray ( 0 to 1 , 0 to 7 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
Generic

Definition at line 32 of file AxiLtc2270Core.vhd.

◆ IODELAY_GROUP_G

IODELAY_GROUP_G string := " AXI_LTC2270_IODELAY_GRP "
Generic

Definition at line 33 of file AxiLtc2270Core.vhd.

◆ STATUS_CNT_WIDTH_G

STATUS_CNT_WIDTH_G natural range 1 to 32 := 32
Generic

Definition at line 34 of file AxiLtc2270Core.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 35 of file AxiLtc2270Core.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 36 of file AxiLtc2270Core.vhd.

◆ adcIn

adcIn in AxiLtc2270InType
Port

Definition at line 39 of file AxiLtc2270Core.vhd.

◆ adcOut

adcOut out AxiLtc2270OutType
Port

Definition at line 40 of file AxiLtc2270Core.vhd.

◆ adcInOut

adcInOut inout AxiLtc2270InOutType
Port

Definition at line 41 of file AxiLtc2270Core.vhd.

◆ adcValid

adcValid out slv ( 0 to 1 )
Port

Definition at line 43 of file AxiLtc2270Core.vhd.

◆ adcData

adcData out Slv16Array ( 0 to 1 )
Port

Definition at line 44 of file AxiLtc2270Core.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 46 of file AxiLtc2270Core.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 47 of file AxiLtc2270Core.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 48 of file AxiLtc2270Core.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 49 of file AxiLtc2270Core.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 51 of file AxiLtc2270Core.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 52 of file AxiLtc2270Core.vhd.

◆ adcClk

adcClk in sl
Port

Definition at line 53 of file AxiLtc2270Core.vhd.

◆ refclk200MHz

refclk200MHz in sl
Port

Definition at line 54 of file AxiLtc2270Core.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiLtc2270Core.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiLtc2270Core.vhd.

◆ numeric_std

numeric_std
Package

Definition at line 20 of file AxiLtc2270Core.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 22 of file AxiLtc2270Core.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 23 of file AxiLtc2270Core.vhd.

◆ AxiLtc2270Pkg

AxiLtc2270Pkg
Package

Definition at line 24 of file AxiLtc2270Core.vhd.

The documentation for this class was generated from the following file: