SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiLiteSrpV0 Entity Reference
protocols » srp
+ Inheritance diagram for AxiLiteSrpV0:
+ Collaboration diagram for AxiLiteSrpV0:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
AXIL_ERR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
RESP_THOLD_G  integer range 0 to ( 2 ** 24 ) := 1
SLAVE_READY_EN_G  boolean := false
BRAM_EN_G  boolean := true
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
GEN_SYNC_FIFO_G  boolean := false
FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 9
FIFO_PAUSE_THRESH_G  integer range 1 to ( 2 ** 24 ) := 2 ** 8
AXI_STREAM_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C

Ports

mAxisClk   in sl
mAxisRst   in sl := ' 0 '
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
sAxisClk   in sl
sAxisRst   in sl := ' 0 '
sAxisMaster   in AxiStreamMasterType
sAxisSlave   out AxiStreamSlaveType
sAxisCtrl   out AxiStreamCtrlType
axilClk   in sl
axilRst   in sl
sAxilWriteMaster   in AxiLiteWriteMasterType
sAxilWriteSlave   out AxiLiteWriteSlaveType
sAxilReadMaster   in AxiLiteReadMasterType
sAxilReadSlave   out AxiLiteReadSlaveType

Detailed Description

See also
entity

Definition at line 35 of file AxiLiteSrpV0.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 38 of file AxiLiteSrpV0.vhd.

◆ AXIL_ERR_RESP_G

AXIL_ERR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 40 of file AxiLiteSrpV0.vhd.

◆ RESP_THOLD_G

RESP_THOLD_G integer range 0 to ( 2 ** 24 ) := 1
Generic

Definition at line 43 of file AxiLiteSrpV0.vhd.

◆ SLAVE_READY_EN_G

SLAVE_READY_EN_G boolean := false
Generic

Definition at line 44 of file AxiLiteSrpV0.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 45 of file AxiLiteSrpV0.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 46 of file AxiLiteSrpV0.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 47 of file AxiLiteSrpV0.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 48 of file AxiLiteSrpV0.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 49 of file AxiLiteSrpV0.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 50 of file AxiLiteSrpV0.vhd.

◆ FIFO_ADDR_WIDTH_G

FIFO_ADDR_WIDTH_G integer range 4 to 48 := 9
Generic

Definition at line 51 of file AxiLiteSrpV0.vhd.

◆ FIFO_PAUSE_THRESH_G

FIFO_PAUSE_THRESH_G integer range 1 to ( 2 ** 24 ) := 2 ** 8
Generic

Definition at line 52 of file AxiLiteSrpV0.vhd.

◆ AXI_STREAM_CONFIG_G

AXI_STREAM_CONFIG_G AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Generic

Definition at line 55 of file AxiLiteSrpV0.vhd.

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 59 of file AxiLiteSrpV0.vhd.

◆ mAxisRst

mAxisRst in sl := ' 0 '
Port

Definition at line 60 of file AxiLiteSrpV0.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 61 of file AxiLiteSrpV0.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType
Port

Definition at line 62 of file AxiLiteSrpV0.vhd.

◆ sAxisClk

sAxisClk in sl
Port

Definition at line 65 of file AxiLiteSrpV0.vhd.

◆ sAxisRst

sAxisRst in sl := ' 0 '
Port

Definition at line 66 of file AxiLiteSrpV0.vhd.

◆ sAxisMaster

sAxisMaster in AxiStreamMasterType
Port

Definition at line 67 of file AxiLiteSrpV0.vhd.

◆ sAxisSlave

sAxisSlave out AxiStreamSlaveType
Port

Definition at line 68 of file AxiLiteSrpV0.vhd.

◆ sAxisCtrl

sAxisCtrl out AxiStreamCtrlType
Port

Definition at line 69 of file AxiLiteSrpV0.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 72 of file AxiLiteSrpV0.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 73 of file AxiLiteSrpV0.vhd.

◆ sAxilWriteMaster

sAxilWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 74 of file AxiLiteSrpV0.vhd.

◆ sAxilWriteSlave

sAxilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 75 of file AxiLiteSrpV0.vhd.

◆ sAxilReadMaster

sAxilReadMaster in AxiLiteReadMasterType
Port

Definition at line 76 of file AxiLiteSrpV0.vhd.

◆ sAxilReadSlave

sAxilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 78 of file AxiLiteSrpV0.vhd.

◆ ieee

ieee
Library

Definition at line 23 of file AxiLiteSrpV0.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 24 of file AxiLiteSrpV0.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 25 of file AxiLiteSrpV0.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 26 of file AxiLiteSrpV0.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 28 of file AxiLiteSrpV0.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 29 of file AxiLiteSrpV0.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 30 of file AxiLiteSrpV0.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 31 of file AxiLiteSrpV0.vhd.

The documentation for this class was generated from the following file: