SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiLiteSaciMaster Entity Reference
protocols » saci
+ Inheritance diagram for AxiLiteSaciMaster:
+ Collaboration diagram for AxiLiteSaciMaster:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
SaciMasterPkg  Package <SaciMasterPkg>

Generics

TPD_G  time := 1 ns
AXIL_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
AXIL_CLK_PERIOD_G  real := 8 . 0e - 9
AXIL_TIMEOUT_G  real := 1 . 0E - 3
SACI_CLK_PERIOD_G  real := 1 . 0e - 6
SACI_CLK_FREERUN_G  boolean := false
SACI_NUM_CHIPS_G  positive range 1 to 4 := 1
SACI_RSP_BUSSED_G  boolean := false

Ports

saciClk   out sl
saciCmd   out sl
saciSelL   out slv ( SACI_NUM_CHIPS_G - 1 downto 0 )
saciRsp   in slv ( ite ( SACI_RSP_BUSSED_G , 0 , SACI_NUM_CHIPS_G - 1 ) downto 0 )
axilClk   in sl
axilRst   in sl
axilReadMaster   in AxiLiteReadMasterType
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType
axilWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 29 of file AxiLiteSaciMaster.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file AxiLiteSaciMaster.vhd.

◆ AXIL_ERROR_RESP_G

AXIL_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 32 of file AxiLiteSaciMaster.vhd.

◆ AXIL_CLK_PERIOD_G

AXIL_CLK_PERIOD_G real := 8 . 0e - 9
Generic

Definition at line 33 of file AxiLiteSaciMaster.vhd.

◆ AXIL_TIMEOUT_G

AXIL_TIMEOUT_G real := 1 . 0E - 3
Generic

Definition at line 34 of file AxiLiteSaciMaster.vhd.

◆ SACI_CLK_PERIOD_G

SACI_CLK_PERIOD_G real := 1 . 0e - 6
Generic

Definition at line 35 of file AxiLiteSaciMaster.vhd.

◆ SACI_CLK_FREERUN_G

SACI_CLK_FREERUN_G boolean := false
Generic

Definition at line 36 of file AxiLiteSaciMaster.vhd.

◆ SACI_NUM_CHIPS_G

SACI_NUM_CHIPS_G positive range 1 to 4 := 1
Generic

Definition at line 37 of file AxiLiteSaciMaster.vhd.

◆ SACI_RSP_BUSSED_G

SACI_RSP_BUSSED_G boolean := false
Generic

Definition at line 38 of file AxiLiteSaciMaster.vhd.

◆ saciClk

saciClk out sl
Port

Definition at line 41 of file AxiLiteSaciMaster.vhd.

◆ saciCmd

saciCmd out sl
Port

Definition at line 42 of file AxiLiteSaciMaster.vhd.

◆ saciSelL

saciSelL out slv ( SACI_NUM_CHIPS_G - 1 downto 0 )
Port

Definition at line 43 of file AxiLiteSaciMaster.vhd.

◆ saciRsp

saciRsp in slv ( ite ( SACI_RSP_BUSSED_G , 0 , SACI_NUM_CHIPS_G - 1 ) downto 0 )
Port

Definition at line 44 of file AxiLiteSaciMaster.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 46 of file AxiLiteSaciMaster.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 47 of file AxiLiteSaciMaster.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType
Port

Definition at line 48 of file AxiLiteSaciMaster.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 49 of file AxiLiteSaciMaster.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 50 of file AxiLiteSaciMaster.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 51 of file AxiLiteSaciMaster.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiLiteSaciMaster.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiLiteSaciMaster.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 20 of file AxiLiteSaciMaster.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file AxiLiteSaciMaster.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiLiteSaciMaster.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiLiteSaciMaster.vhd.

◆ SaciMasterPkg

SaciMasterPkg
Package

Definition at line 25 of file AxiLiteSaciMaster.vhd.

The documentation for this class was generated from the following file: