SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiLiteRingBuffer Entity Reference
axi
+ Inheritance diagram for AxiLiteRingBuffer:
+ Collaboration diagram for AxiLiteRingBuffer:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
BRAM_EN_G  boolean := true
REG_EN_G  boolean := true
DATA_WIDTH_G  positive range 1 to 32 := 32
RAM_ADDR_WIDTH_G  positive range 1 to 19 := 10
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C

Ports

dataClk   in sl
dataRst   in sl := ' 0 '
dataValid   in sl := ' 1 '
dataValue   in slv ( DATA_WIDTH_G - 1 downto 0 )
bufferEnable   in sl := ' 0 '
bufferClear   in sl := ' 0 '
axilClk   in sl
axilRst   in sl
axilReadMaster   in AxiLiteReadMasterType
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType
axilWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 28 of file AxiLiteRingBuffer.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file AxiLiteRingBuffer.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 32 of file AxiLiteRingBuffer.vhd.

◆ REG_EN_G

REG_EN_G boolean := true
Generic

Definition at line 33 of file AxiLiteRingBuffer.vhd.

◆ DATA_WIDTH_G

DATA_WIDTH_G positive range 1 to 32 := 32
Generic

Definition at line 34 of file AxiLiteRingBuffer.vhd.

◆ RAM_ADDR_WIDTH_G

RAM_ADDR_WIDTH_G positive range 1 to 19 := 10
Generic

Definition at line 35 of file AxiLiteRingBuffer.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 36 of file AxiLiteRingBuffer.vhd.

◆ dataClk

dataClk in sl
Port

Definition at line 39 of file AxiLiteRingBuffer.vhd.

◆ dataRst

dataRst in sl := ' 0 '
Port

Definition at line 40 of file AxiLiteRingBuffer.vhd.

◆ dataValid

dataValid in sl := ' 1 '
Port

Definition at line 41 of file AxiLiteRingBuffer.vhd.

◆ dataValue

dataValue in slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 42 of file AxiLiteRingBuffer.vhd.

◆ bufferEnable

bufferEnable in sl := ' 0 '
Port

Definition at line 43 of file AxiLiteRingBuffer.vhd.

◆ bufferClear

bufferClear in sl := ' 0 '
Port

Definition at line 44 of file AxiLiteRingBuffer.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 46 of file AxiLiteRingBuffer.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 47 of file AxiLiteRingBuffer.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType
Port

Definition at line 48 of file AxiLiteRingBuffer.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 49 of file AxiLiteRingBuffer.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 50 of file AxiLiteRingBuffer.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 51 of file AxiLiteRingBuffer.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiLiteRingBuffer.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiLiteRingBuffer.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file AxiLiteRingBuffer.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file AxiLiteRingBuffer.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file AxiLiteRingBuffer.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file AxiLiteRingBuffer.vhd.

The documentation for this class was generated from the following file: