SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiLiteFifoPop Entity Reference
axi
+ Inheritance diagram for AxiLiteFifoPop:
+ Collaboration diagram for AxiLiteFifoPop:

Entities

structure  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
STD_LOGIC_ARITH 
STD_LOGIC_UNSIGNED 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
POP_FIFO_COUNT_G  positive := 1
POP_SYNC_FIFO_G  boolean := false
POP_BRAM_EN_G  boolean := true
POP_ADDR_WIDTH_G  integer range 4 to 48 := 4
POP_FULL_THRES_G  integer range 1 to ( 2 ** 24 ) := 1
LOOP_FIFO_EN_G  boolean := false
LOOP_FIFO_COUNT_G  positive := 1
LOOP_BRAM_EN_G  boolean := true
LOOP_ADDR_WIDTH_G  integer range 4 to 48 := 4
RANGE_LSB_G  integer range 0 to 31 := 8
VALID_POSITION_G  integer range 0 to 31 := 0
VALID_POLARITY_G  sl := ' 0 '
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
USE_BUILT_IN_G  boolean := false
XIL_DEVICE_G  string := " 7SERIES "

Ports

axiClk   in sl
axiClkRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiWriteSlave   out AxiLiteWriteSlaveType
popFifoValid   out slv ( POP_FIFO_COUNT_G - 1 downto 0 )
popFifoAEmpty   out slv ( POP_FIFO_COUNT_G - 1 downto 0 )
loopFifoValid   out slv ( LOOP_FIFO_COUNT_G - 1 downto 0 )
loopFifoAEmpty   out slv ( LOOP_FIFO_COUNT_G - 1 downto 0 )
loopFifoAFull   out slv ( LOOP_FIFO_COUNT_G - 1 downto 0 )
popFifoClk   in slv ( POP_FIFO_COUNT_G - 1 downto 0 )
popFifoRst   in slv ( POP_FIFO_COUNT_G - 1 downto 0 )
popFifoWrite   in slv ( POP_FIFO_COUNT_G - 1 downto 0 )
popFifoDin   in Slv32Array ( POP_FIFO_COUNT_G - 1 downto 0 )
popFifoFull   out slv ( POP_FIFO_COUNT_G - 1 downto 0 )
popFifoAFull   out slv ( POP_FIFO_COUNT_G - 1 downto 0 )
popFifoPFull   out slv ( POP_FIFO_COUNT_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 30 of file AxiLiteFifoPop.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file AxiLiteFifoPop.vhd.

◆ POP_FIFO_COUNT_G

POP_FIFO_COUNT_G positive := 1
Generic

Definition at line 33 of file AxiLiteFifoPop.vhd.

◆ POP_SYNC_FIFO_G

POP_SYNC_FIFO_G boolean := false
Generic

Definition at line 34 of file AxiLiteFifoPop.vhd.

◆ POP_BRAM_EN_G

POP_BRAM_EN_G boolean := true
Generic

Definition at line 35 of file AxiLiteFifoPop.vhd.

◆ POP_ADDR_WIDTH_G

POP_ADDR_WIDTH_G integer range 4 to 48 := 4
Generic

Definition at line 36 of file AxiLiteFifoPop.vhd.

◆ POP_FULL_THRES_G

POP_FULL_THRES_G integer range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 37 of file AxiLiteFifoPop.vhd.

◆ LOOP_FIFO_EN_G

LOOP_FIFO_EN_G boolean := false
Generic

Definition at line 38 of file AxiLiteFifoPop.vhd.

◆ LOOP_FIFO_COUNT_G

LOOP_FIFO_COUNT_G positive := 1
Generic

Definition at line 39 of file AxiLiteFifoPop.vhd.

◆ LOOP_BRAM_EN_G

LOOP_BRAM_EN_G boolean := true
Generic

Definition at line 40 of file AxiLiteFifoPop.vhd.

◆ LOOP_ADDR_WIDTH_G

LOOP_ADDR_WIDTH_G integer range 4 to 48 := 4
Generic

Definition at line 41 of file AxiLiteFifoPop.vhd.

◆ RANGE_LSB_G

RANGE_LSB_G integer range 0 to 31 := 8
Generic

Definition at line 42 of file AxiLiteFifoPop.vhd.

◆ VALID_POSITION_G

VALID_POSITION_G integer range 0 to 31 := 0
Generic

Definition at line 43 of file AxiLiteFifoPop.vhd.

◆ VALID_POLARITY_G

VALID_POLARITY_G sl := ' 0 '
Generic

Definition at line 44 of file AxiLiteFifoPop.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 45 of file AxiLiteFifoPop.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 46 of file AxiLiteFifoPop.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 47 of file AxiLiteFifoPop.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 49 of file AxiLiteFifoPop.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 53 of file AxiLiteFifoPop.vhd.

◆ axiClkRst

axiClkRst in sl
Port

Definition at line 54 of file AxiLiteFifoPop.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 55 of file AxiLiteFifoPop.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 56 of file AxiLiteFifoPop.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 57 of file AxiLiteFifoPop.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 58 of file AxiLiteFifoPop.vhd.

◆ popFifoValid

popFifoValid out slv ( POP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 59 of file AxiLiteFifoPop.vhd.

◆ popFifoAEmpty

popFifoAEmpty out slv ( POP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 60 of file AxiLiteFifoPop.vhd.

◆ loopFifoValid

loopFifoValid out slv ( LOOP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 61 of file AxiLiteFifoPop.vhd.

◆ loopFifoAEmpty

loopFifoAEmpty out slv ( LOOP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 62 of file AxiLiteFifoPop.vhd.

◆ loopFifoAFull

loopFifoAFull out slv ( LOOP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 63 of file AxiLiteFifoPop.vhd.

◆ popFifoClk

popFifoClk in slv ( POP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 66 of file AxiLiteFifoPop.vhd.

◆ popFifoRst

popFifoRst in slv ( POP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 67 of file AxiLiteFifoPop.vhd.

◆ popFifoWrite

popFifoWrite in slv ( POP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 68 of file AxiLiteFifoPop.vhd.

◆ popFifoDin

popFifoDin in Slv32Array ( POP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 69 of file AxiLiteFifoPop.vhd.

◆ popFifoFull

popFifoFull out slv ( POP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 70 of file AxiLiteFifoPop.vhd.

◆ popFifoAFull

popFifoAFull out slv ( POP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 71 of file AxiLiteFifoPop.vhd.

◆ popFifoPFull

popFifoPFull out slv ( POP_FIFO_COUNT_G - 1 downto 0 )
Port

Definition at line 73 of file AxiLiteFifoPop.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file AxiLiteFifoPop.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 21 of file AxiLiteFifoPop.vhd.

◆ STD_LOGIC_ARITH

STD_LOGIC_ARITH
Package

Definition at line 22 of file AxiLiteFifoPop.vhd.

◆ STD_LOGIC_UNSIGNED

STD_LOGIC_UNSIGNED
Package

Definition at line 23 of file AxiLiteFifoPop.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 25 of file AxiLiteFifoPop.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 26 of file AxiLiteFifoPop.vhd.

The documentation for this class was generated from the following file: