SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiLiteEmpty Entity Reference
axi
+ Inheritance diagram for AxiLiteEmpty:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_OK_C
NUM_WRITE_REG_G  integer range 1 to 32 := 1
NUM_READ_REG_G  integer range 1 to 32 := 1

Ports

axiClk   in sl
axiClkRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
writeRegister   out Slv32Array ( NUM_WRITE_REG_G - 1 downto 0 )
readRegister   in Slv32Array ( NUM_READ_REG_G - 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )

Detailed Description

See also
entity

Definition at line 34 of file AxiLiteEmpty.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 36 of file AxiLiteEmpty.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_OK_C
Generic

Definition at line 37 of file AxiLiteEmpty.vhd.

◆ NUM_WRITE_REG_G

NUM_WRITE_REG_G integer range 1 to 32 := 1
Generic

Definition at line 38 of file AxiLiteEmpty.vhd.

◆ NUM_READ_REG_G

NUM_READ_REG_G integer range 1 to 32 := 1
Generic

Definition at line 39 of file AxiLiteEmpty.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 42 of file AxiLiteEmpty.vhd.

◆ axiClkRst

axiClkRst in sl
Port

Definition at line 43 of file AxiLiteEmpty.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 44 of file AxiLiteEmpty.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 45 of file AxiLiteEmpty.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 46 of file AxiLiteEmpty.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 47 of file AxiLiteEmpty.vhd.

◆ writeRegister

writeRegister out Slv32Array ( NUM_WRITE_REG_G - 1 downto 0 )
Port

Definition at line 49 of file AxiLiteEmpty.vhd.

◆ readRegister

readRegister in Slv32Array ( NUM_READ_REG_G - 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
Port

Definition at line 50 of file AxiLiteEmpty.vhd.

◆ ieee

ieee
Library

Definition at line 24 of file AxiLiteEmpty.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 25 of file AxiLiteEmpty.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 26 of file AxiLiteEmpty.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 27 of file AxiLiteEmpty.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 29 of file AxiLiteEmpty.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 30 of file AxiLiteEmpty.vhd.

The documentation for this class was generated from the following file: