SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiI2cQsfpCore Entity Reference
devices » transceivers » qsfp
+ Inheritance diagram for AxiI2cQsfpCore:
+ Collaboration diagram for AxiI2cQsfpCore:

Entities

mapping  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
numeric_std 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
I2cPkg  Package <I2cPkg>
AxiI2cQsfpPkg  Package <AxiI2cQsfpPkg>
vcomponents 

Generics

TPD_G  time := 1 ns
AXI_CLK_FREQ_G  real := 200 . 0E + 6
I2C_SCL_FREQ_G  real := 100 . 0E + 3
I2C_MIN_PULSE_G  real := 100 . 0E - 9
STATUS_CNT_WIDTH_G  natural range 1 to 32 := 32
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

qsfpIn   in AxiI2cQsfpInType
qsfpInOut   inout AxiI2cQsfpInOutType
qsfpOut   out AxiI2cQsfpOutType
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
axiClk   in sl
axiRst   in sl

Detailed Description

See also
entity

Definition at line 32 of file AxiI2cQsfpCore.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 34 of file AxiI2cQsfpCore.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 200 . 0E + 6
Generic

Definition at line 35 of file AxiI2cQsfpCore.vhd.

◆ I2C_SCL_FREQ_G

I2C_SCL_FREQ_G real := 100 . 0E + 3
Generic

Definition at line 36 of file AxiI2cQsfpCore.vhd.

◆ I2C_MIN_PULSE_G

I2C_MIN_PULSE_G real := 100 . 0E - 9
Generic

Definition at line 37 of file AxiI2cQsfpCore.vhd.

◆ STATUS_CNT_WIDTH_G

STATUS_CNT_WIDTH_G natural range 1 to 32 := 32
Generic

Definition at line 38 of file AxiI2cQsfpCore.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 39 of file AxiI2cQsfpCore.vhd.

◆ qsfpIn

qsfpIn in AxiI2cQsfpInType
Port

Definition at line 42 of file AxiI2cQsfpCore.vhd.

◆ qsfpInOut

qsfpInOut inout AxiI2cQsfpInOutType
Port

Definition at line 43 of file AxiI2cQsfpCore.vhd.

◆ qsfpOut

qsfpOut out AxiI2cQsfpOutType
Port

Definition at line 44 of file AxiI2cQsfpCore.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 46 of file AxiI2cQsfpCore.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 47 of file AxiI2cQsfpCore.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 48 of file AxiI2cQsfpCore.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 49 of file AxiI2cQsfpCore.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 51 of file AxiI2cQsfpCore.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 52 of file AxiI2cQsfpCore.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file AxiI2cQsfpCore.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file AxiI2cQsfpCore.vhd.

◆ numeric_std

numeric_std
Package

Definition at line 20 of file AxiI2cQsfpCore.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 22 of file AxiI2cQsfpCore.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 23 of file AxiI2cQsfpCore.vhd.

◆ I2cPkg

I2cPkg
Package

Definition at line 24 of file AxiI2cQsfpCore.vhd.

◆ AxiI2cQsfpPkg

AxiI2cQsfpPkg
Package

Definition at line 25 of file AxiI2cQsfpCore.vhd.

◆ unisim

unisim
Library

Definition at line 27 of file AxiI2cQsfpCore.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 28 of file AxiI2cQsfpCore.vhd.

The documentation for this class was generated from the following file: