SURF  1.0
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AxiI2cEeprom Entity Reference
protocols » i2c
+ Inheritance diagram for AxiI2cEeprom:
+ Collaboration diagram for AxiI2cEeprom:

Entities

mapping  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
I2cPkg  Package <I2cPkg>
vcomponents 

Generics

TPD_G  time := 1 ns
ADDR_WIDTH_G  positive := 16
POLL_TIMEOUT_G  positive := 16
I2C_ADDR_G  slv ( 6 downto 0 ) := " 1010000 "
I2C_SCL_FREQ_G  real := 100 . 0E + 3
I2C_MIN_PULSE_G  real := 100 . 0E - 9
AXI_CLK_FREQ_G  real := 156 . 25E + 6
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C

Ports

scl   inout sl
sda   inout sl
axilReadMaster   in AxiLiteReadMasterType
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType
axilWriteSlave   out AxiLiteWriteSlaveType
axilClk   in sl
axilRst   in sl

Detailed Description

See also
entity

Definition at line 42 of file AxiI2cEeprom.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 44 of file AxiI2cEeprom.vhd.

◆ ADDR_WIDTH_G

ADDR_WIDTH_G positive := 16
Generic

Definition at line 45 of file AxiI2cEeprom.vhd.

◆ POLL_TIMEOUT_G

POLL_TIMEOUT_G positive := 16
Generic

Definition at line 46 of file AxiI2cEeprom.vhd.

◆ I2C_ADDR_G

I2C_ADDR_G slv ( 6 downto 0 ) := " 1010000 "
Generic

Definition at line 47 of file AxiI2cEeprom.vhd.

◆ I2C_SCL_FREQ_G

I2C_SCL_FREQ_G real := 100 . 0E + 3
Generic

Definition at line 48 of file AxiI2cEeprom.vhd.

◆ I2C_MIN_PULSE_G

I2C_MIN_PULSE_G real := 100 . 0E - 9
Generic

Definition at line 49 of file AxiI2cEeprom.vhd.

◆ AXI_CLK_FREQ_G

AXI_CLK_FREQ_G real := 156 . 25E + 6
Generic

Definition at line 50 of file AxiI2cEeprom.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 51 of file AxiI2cEeprom.vhd.

◆ scl

scl inout sl
Port

Definition at line 54 of file AxiI2cEeprom.vhd.

◆ sda

sda inout sl
Port

Definition at line 55 of file AxiI2cEeprom.vhd.

◆ axilReadMaster

axilReadMaster in AxiLiteReadMasterType
Port

Definition at line 57 of file AxiI2cEeprom.vhd.

◆ axilReadSlave

axilReadSlave out AxiLiteReadSlaveType
Port

Definition at line 58 of file AxiI2cEeprom.vhd.

◆ axilWriteMaster

axilWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 59 of file AxiI2cEeprom.vhd.

◆ axilWriteSlave

axilWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 60 of file AxiI2cEeprom.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 62 of file AxiI2cEeprom.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 63 of file AxiI2cEeprom.vhd.

◆ ieee

ieee
Library

Definition at line 30 of file AxiI2cEeprom.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 31 of file AxiI2cEeprom.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 33 of file AxiI2cEeprom.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 34 of file AxiI2cEeprom.vhd.

◆ I2cPkg

I2cPkg
Package

Definition at line 35 of file AxiI2cEeprom.vhd.

◆ unisim

unisim
Library

Definition at line 37 of file AxiI2cEeprom.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 38 of file AxiI2cEeprom.vhd.

The documentation for this class was generated from the following file: